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8th international Workshop on High-Level parallel Programming Models and Supportive Environments, HIPS 2003, Held in conjunction with 17th international parallel and Distributed processing Symposium, IPDPS 2003

ISBN: (纸本)076951880X

the proceedings contain 9 papers. the topics discussed include: supporting peer-2-peer interactions in the consumer grid;DPS - dynamic parallel schedules;ParoC++: a requirement-driven parallel object-oriented programming language;on the implementation of JavaSymphony;compiler and runtime support for running OpenMP programs on Pentium- and Itanium-architectures;SMP-aware message passing programming;a comparison between MPI and OpenMP branch-and-bound skeletons;a comparison between MPI and OpenMP branch-and-bound skeletons;and algorithmic concept recognition support for skeleton based parallel programming.

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5th international conference on parallel processing and Applied Mathematics, PPAM 2003

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5th international conference on parallel processing and Applied Mathematics, PPAM 2003

ISBN: (纸本)3540219463

the proceedings contain 149 papers. the special focus in this conference is on parallel, Distributed architectures, Scheduling and Load Balancing. the topics include: Session guarantees to achieve pram consistency of replicated shared objects;an extended atomic consistency protocol for recoverable DSM systems;hyper-threading technology speeds clusters;configurable microprocessor array for DSP applications;on generalized moore digraphs;RDMA communication based on rotating buffers for efficient parallel fine-grain computations;communication on the fly in dynamic SMP clusters;accelerated diffusion algorithms on general dynamic networks;suitability of load scheduling algorithms to workload characteristics;minimizing time-dependent total completion time on parallel identical machines;diffusion based scheduling in the agent-oriented computing system;approximation algorithms for scheduling jobs with chain precedence constraints;combining vector quantization and ant-colony algorithm for mesh-partitioning;wavelet-neuronal resource load prediction for multiprocessor environment;fault-tolerant scheduling in distributed real-time systems;online scheduling of multiprocessor jobs with idle regulation;predicting the response time of a new task on a beowulf cluster;space decomposition solvers and their performance in pc-based parallel computing environments;evaluation of execution time of mathematical library functions based on historical performance information;empirical modelling of parallel linear algebra routines;efficiency of divisible load processing;gray box based data access time estimation for tertiary storage in grid environment;performance modeling of parallel fem computations on clusters;asymptotical behaviour of the communication complexity of one parallel algorithm and analytical modeling of optimized sparse linear code.

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Linear Predictive method with Low-Frequency Emphasis 8

Linear Predictive method with Low-Frequency Emphasis

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8th European conference on Speech Communication and Technology, EUROSPEECH 2003

作者： Alku, Paavo Bäckström, Tom Lab. of Acoustics and Audio Signal Processing Helsinki University of Technology Finland

An all-pole modeling technique, Linear Prediction with Low-frequency Emphasis (LPLE), which emphasizes the lower frequency range of speech, is presented. the method is based on first interpreting conventional linear predictive (LP) analyses of successive prediction orders with parallel structures using the concept of symmetric linear prediction. In these implementations, symmetric linear prediction is preceded by simple pre-filters, which are of either low or high frequency characteristics. Combining those symmetric linear predictors that are not preceded by high-frequency pre-filters yields the LPLE predictor. It is proved that the all-pole filters computed by LPLE are always stable. the results show that the method is well-suited when low-order all-pole models with improved modeling of the lowest formants are needed.

关键词： Forecasting

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8th Panhellenic conference on Informatics, PCI 2001

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8th Panhellenic conference on Informatics, PCI 2001

ISBN: (纸本)9783540075448

the proceedings contain 31 papers. the special focus in this conference is on Informatics. the topics include: processing distance-based queries in multidimensional data spaces using r-trees;a simple, compact and dynamic partition scheme based on co-centric spheres;materialized views for data warehouses and the web;two-phase commit processing with restructured commit tree;on the use of matrices for belief revision;efficiently maintaining structural associations of semistructured data;identification of lead compounds in pharmaceutical data using data mining techniques;a prototype for collecting, querying, and mining seismic data;using fuzzy cognitive maps as a decision support system for political decisions;an architecture for open learning management systems;a knowledge based approach on educational metadata use;concepts to consider when studying computer-mediated communication and online learning;website content accessibility of the cyprus domain;an information hiding method based on computational intractable problems;an experimental evaluation of a monte-carlo algorithm for singular value decomposition;an integrated environment for task allocation and execution of MPI applications onto parallel architectures;communication assist for data driven multithreading;high level timed petri net templates for the temporal verification of real-time multiprocessor applications;a Greek morphological lexicon and its exploitation by natural language processing applications;a comparison of design patterns and roles in the context of behavioural evolution;a new randomized data structure for the 1 1/2-dimensional range query problem;acceptor-definable counting classes and stability behavior of fifo protocol in the adversarial queuing model.

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Performance analysis and qualitative results of an efficient parallel stochastic simulator for a marine host-parasite system

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2003年第11-12期15卷 1133-1150页

作者： Langlais, M Latu, G Roman, J Silan, P Univ Bordeaux 1 CNRS UMR 5800 LaBRI F-33405 Talence France ENSEIRB F-33405 Talence France Univ Bordeaux 2 CNRS UMR 5466 MAB F-33076 Bordeaux France Univ Montpellier 2 CNRS UMR 5000 F-34200 Sete France

We are interested in a host-parasite system, i.e. the sea bass-Diplectanum aequans system. A discrete mathematical model is used to describe the dynamics of both populations. Our goal is notably to validate the model in the context of aquaculture. A deterministic numerical simulator and, recently, a stochastic simulator were developed to study this biological system. parallelization is required because the execution times are too long. the Monte Carlo algorithm of the stochastic simulator and its three levels of parallelism are described. Analysis and performances, up to 256 processors, of a hybrid MPI/OpenMP code are then presented for a cluster of symmetric multi-processor (SMP) nodes. Qualitative results are given for the host-macroparasite system simulation. Copyright (C) 2003 John Wiley Sons, Ltd.

关键词： parallel algorithmics numerical simulation stochastic simulation host-parasite system Monogenea fish

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SCALEA: a performance analysis tool for parallel programs

SCALEA: a performance analysis tool for parallel programs

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8th international Euro-Par conference on parallel processing

作者： Truong, HL Fahringer, T Univ Vienna Inst Software Sci A-1090 Vienna Austria

Many existing performance analysis tools lack the flexibility to control instrumentation and performance measurement for code regions and performance metrics of interest. Performance analysis is commonly restricted to single experiments. In this paper we present SCALEA, which is a performance instrumentation, measurement, analysis, and visualization tool for parallel programs that supports post-mortem performance analysis. SCALEA currently focuses on performance analysis for OpenMP, MPI, HPF, and mixed parallel programs. It computes a variety of performance metrics based on a novel classification of overhead. SCALEA also supports multi-experiment performance analysis that allows one to compare and to evaluate the performance outcome of several experiments. A highly flexible instrumentation and measurement system is provided which can be controlled by command-line options and program directives. SCALEA can be interfaced by external tools through the provision of a full Fortran90 OpenMP/MPI/HPF frontend that allows one to instrument an abstract syntax tree at a very high-level with C-function calls and to generate source code. A graphical user interface is provided to view a large variety of performance metrics at the level of arbitrary code regions, threads, processes, and computational nodes for single- and multi-experiment performance analysis. Copyright (C) 2003 John Wiley Sons, Ltd.

关键词： performance analysis instrumentation performance overheads visualization parallel programs

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Performance analysis and qualitative results of an efficient parallel stochastic simulator for a marine host-parasite system

Performance analysis and qualitative results of an efficient...

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8th international Euro-Par conference on parallel processing

关键词： parallel algorithmics numerical simulation stochastic simulation host-parasite system Monogenea fish

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Implementation of a highly scalable architecture for fast inversion of triangular matrices

Implementation of a highly scalable architecture for fast in...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： F. Edman V. Owall Department of Electroscience Lund University Sweden

In this paper, an FPGA implementation of a novel and highly scalable hardware architecture for fast inversion of triangular matrices is presented. An integral part of modem signal processing and communications applications involves manipulation of large matrices. therefore, scalable and flexible hardware architectures are increasingly sought for. In this paper, the traditional triangular shaped array architecture with n(n+l)/2 communicating processors, with n being the number of inputs, is mapped to a linear structure with only n processors. the linear and the triangular shaped architectures are compared in aspect of area consumption, latencies, and maximum clocking speed. this paper also show that the linear array structure avoids drawbacks such as non-scalability, large area, and large power consumption. the implementation is based on a numerically stable recurrence algorithm, which has excellent properties for hardware implementation.

关键词： Signal processing algorithms Hardware Clocks Array signal processing Energy consumption parallel processing Computer architecture Modems Delay throughput

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A fast parallel Reed-Solomon decoder on a reconfigurable architecture 03

A fast parallel Reed-Solomon decoder on a reconfigurable arc...

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international conference on Hardware/Software Codesign and System Synthesis (CODES)

作者： A. Koohi Nader Bagherzadeh Chengzi Pan EECS Department University of California Irvine USA

ISBN: (纸本)9781581137422

this paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targeting on streamed applications such as multimedia and DSP. Numerous modifications of the first-generation of the architecture have made a scalable computation and communication intensive architecture capable of extracting parallelisms of fine grain in instruction level. Many algorithms and the whole digital video broadcasting base-band receiver as well, have been mapped onto the second architecture with impressive performance. the mapping of a Reed-Solomon decoder proposed in the paper highly parallelizes all of its sub-algorithms, including Syndrome Computation, Berlekamp Algorithm, Chein Search, and Error Value Computation, in a SIMD fashion. the mapping is tested on a cycle-accurate simulator, "Mulate", and the performance is encouragingly better than other architectures. the decoding speed of the RS (255,239,16) decoder using two different methods of GF multiplication can be 1.319 Gbps and 2.534 Gbps, respectively. Furthermore, since there is no functionality specifically tailored to Reed-Solomon decoder, the result has demonstrated the capability of MorphoSys architecture to extracting instruction level parallelism from streamed applications.

关键词： Reed-Solomon codes Decoding Reconfigurable architectures Concurrent computing Computer architecture Streaming media parallel processing Application software Digital signal processing Computer aided instruction

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Mapping and scheduling for architecture exploration of networking SoCs

Mapping and scheduling for architecture exploration of netwo...

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international conference on VLSI Design

作者： T. Wild J. Foag N. Pazos W. Brunnbauer Institute for Integrated Circuits Technical University Munich Munich Germany System Architecture Group Communications Infineon Technologies North America Corporation San Jose CA USA

Describes two different approaches to optimize the performance of SoC architectures in the architecture exploration phase. Both solve the problem to map and schedule a task graph on a target architecture under special consideration of on-chip communications. A constructive algorithm is presented that extends previous work by taking into account potential data transfers in the future. the second approach is a recursive procedure that is based on local search techniques in a specially defined neighborhood of the critical path. Simulated annealing and tabu search are used as search algorithms. Both approaches find solutions with better performance than established methodologies. the recursive technique leads to superior results than the constructive approach, however, is limited to small and mid-sized problems, whereas the constructive algorithm is not limited by this issue.

关键词： Scheduling Partitioning algorithms Very large scale integration Delay NP-complete problem Polynomials Constraint optimization parallel processing Proposals Context

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