We study a new design strategy for the implementation of parallel Media Servers with a predictable behavior. this strategy makes the timing properties and the quality of presentation of a set of media streams predicta...
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ISBN:
(纸本)3540440496
We study a new design strategy for the implementation of parallel Media Servers with a predictable behavior. this strategy makes the timing properties and the quality of presentation of a set of media streams predictable. the proposed real-time scheduling approach exploits the performance of parallel environments and seems a promising method that brings the advantages of parallel computation in media servers. the proposed mechanism provides deterministic service for both Constant Bit Rate (CBR) and Variable Bit Rate (VBR) streams. A prototype implementation of the proposed parallel media server illustrates the concepts of server allocation and scheduling of continuous media streams.
Welcome to this topic of the Euro-Par conference held this year in picturesque Paderborn, Germany. I was extremely honored to serve as the global chair for these sessions on parallel Computer Architecture and Instruct...
ISBN:
(纸本)3540440496
Welcome to this topic of the Euro-Par conference held this year in picturesque Paderborn, Germany. I was extremely honored to serve as the global chair for these sessions on parallel Computer Architecture and Instruction-Level parallelism and I look forward to meeting all practitioners of the field, researchers, and students at the conference.
A consensus on a parallel architecture for very large database management has emerged. this architecture is based on a shared-nothing hardware organization. the computation model is very sensitive to skew in tuple dis...
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the mapping of parallel applications constitutes a difficult problem for which very few practical tools are available. AMEEDA has been developed in order to overcome the lack of a general-purpose mapping tool. the aut...
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ISBN:
(纸本)3540440496
the mapping of parallel applications constitutes a difficult problem for which very few practical tools are available. AMEEDA has been developed in order to overcome the lack of a general-purpose mapping tool. the automatic services provided in AMEEDA include instrumentation facilities, parameter extraction modules and mapping strategies. With all these services, and a novel graph formalism called TTIG, users can apply different mapping strategies to the corresponding application through an easy-to-use GUI, and run the application on a PVM cluster using the desired mapping.
the FPGA has provided us low cost yet extremely powerful reconfigurable hardware, which provides excellent scope for the implementation of parallelalgorithms. We propose that despite having this enormous potential at...
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the parallel fuzzy c-means (PFCM) algorithm for clustering large data sets is proposed in this paper. the proposed algorithm is designed to run on parallel computers of the Single Program Multiple Data (SPMD) model ty...
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ISBN:
(纸本)3540440496
the parallel fuzzy c-means (PFCM) algorithm for clustering large data sets is proposed in this paper. the proposed algorithm is designed to run on parallel computers of the Single Program Multiple Data (SPMD) model type withthe Message Passing Interface (MPI). A comparison is made between PFCM and an existing parallel k-means (PKM) algorithm in terms of their paxallelisation capability and scalability. In an implementation of PFCM to cluster a large data set from an insurance company, the proposed algorithm is demonstrated to have almost ideal speedups as well as an excellent scaleup with respect to the size of the data sets.
Atomic Layer Deposition is one step in the industrial manufacturing of semiconductor chips. It is mathematically modeled by the Boltzmann equation of gas dynamics. Using an expansion in velocity space, the Boltzmann e...
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there is wasted and idle computing potential not only when applications are executed, but also when a user navigates by Internet. To take advantage of this, an architecture named Parasite has been designed in order to...
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ISBN:
(纸本)3540440496
there is wasted and idle computing potential not only when applications are executed, but also when a user navigates by Internet. To take advantage of this, an architecture named Parasite has been designed in order to use distributed and networked resources without disturbing the local computation. the project is based on developing software technologies and infrastructures to facilitate Web-based distributed computing. this paper outlines the most recent advances in the project, as well as discussing the developed architecture and an experimental framework in order to validate this infrastructure.
Over the last decade a lot of research and development efforts have gone into designing competitive video coding standards for several kinds of applications. Some video encoders like MPEG-4 and H.26L, exhibit a high c...
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ISBN:
(纸本)3540440496
Over the last decade a lot of research and development efforts have gone into designing competitive video coding standards for several kinds of applications. Some video encoders like MPEG-4 and H.26L, exhibit a high computational cost, far from real-time encoding, with medium to high quality video sequences. So, for these kinds of video coding standards, it is very difficult to find software solutions able to code video in real-time. In this paper, we design a parallel version of the ITU-T H.26L video coding standard, showing different implementation approaches and evaluate their performance.
In this paper, the discrete state space recursive filters are implemented in the form of parallel array processors. the state space description permits the straightforward application of systolic architectures to real...
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ISBN:
(纸本)0780375963
In this paper, the discrete state space recursive filters are implemented in the form of parallel array processors. the state space description permits the straightforward application of systolic architectures to realize recursive filters of 1D and 2D types. We show that the recursivity inherent to the filtering algorithm introduces a latency proportional to the filter order. Morover, we show that the use of CTP decomposition technique together withthe cylindrical-type structures reduces significantly this latency and improves the computation throughput of these arrays. the processing cells of the systolic array are designed via Switched-Capacitor techniques.
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