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检索条件"任意字段=8th International Conference on Algorithms and Architectures for Parallel Processing"

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Multifunctional automaton for computation of disordered Boolean functions

Multifunctional automaton for computation of disordered Bool...

引用

international Scientific and Practical conference of Students, Post-graduates and Young Scientists Modern Technique and Technologies

作者： S.V. Shidlovskiy Tomsk Polytechnic University Russia

One of the promising directions in the complex control and data processing system design is the development of specialized processors for large data arrays with an internal performance of the order of 2 /spl times/ 10/sup 8/ operations per second and the modeling of complex systems executing in parallel and simultaneously complex operations in real time. the relevant nonrecurrent Boolean functions for these systems have been classified previously where multifunctional logic modules (MLM) realizing ordered Boolean functions from the given class were also described. By MLM (module) is meant an adjustable automaton whose output values depend only on the values of its input signals. the present work describes an MLM for computation of disordered functions.

关键词： Automata Boolean functions Circuits Control system synthesis Fast Fourier transforms Signal processing Filtration Concurrent computing Real time systems Instruments

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Decomposition of modular destination graphs for many-many packet routing in multi-link binary hypercubes

Decomposition of modular destination graphs for many-many pa...

引用

international conference on Communication Systems

作者： D.A. Batovski St. Gabriel Telecommunications Laboratory Department of Telecommunications Science Faculty of Science and Technology Assumption University Bangkok Thailand

the paper considers the existence of oblivious many-many packet routing in multi-link binary hypercubes. Modular destination graphs are decomposed according to a certain number of links for a particular dimension n of the hypercube in order to establish conflict-free tight minimum routing within a network cycle consisting of n hops. Quasi-dimension-order routing is applied, where the replacements of the unidentical bit positions between source and destination are cyclic. Sample results of graph decomposition for a number of dimensions n /spl les/ 7 are presented in the Appendix.

关键词： Routing Hypercubes Switching circuits Wavelength division multiplexing Optical interconnections Computer Society Laboratories Optical fiber networks Optical packet switching parallel processing

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Fast software implementation of MPEG advanced audio encoder

Fast software implementation of MPEG advanced audio encoder

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international conference on Digital Signal processing (DSP)

作者： I. Dimkoviae D. Milovanoviae Z. Bojkoviae PsyTEL Research Belgrade Serbia Faculty of Elcclrical Engineering Belgrade Serbia

An optimized software implementation of a high quality MPEG AAC-LC (low complexity) audio encoder is presented in this paper. the standard reference encoder is improved by utilizing several algorithmic optimizations (fast psycho-acoustic model, new tonality estimation, new time domain block switching, optimized quantizer and Huffman coder) and very careful code optimizations for PC CPU architectures with SIMD (single-instruction-multiple-data) instruction set. the psychoacoustic model used the MDCT filterbank for energy estimation and peak detection as a measure of tonality. Block size decision is based on local perceptual entropies as well as LPC analysis of the time signal. Algorithmic optimizations in the quantizer include loop control module modification and optimized Huffman search. Code optimization is based on parallel processing by replacing vector algebra and math junctions with their optimized equivalents with Intel/sup /spl reg// Signal processing Library (SPL). the implemented codec outperforms consumer MP3 encoders at 30% less bitrate at the same time achieving encoding times several times faster than real-time.

关键词： Signal processing algorithms Psychoacoustic models Software quality Code standards Psychology Filter bank Energy measurement Entropy Linear predictive coding Signal analysis

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Analogic cellular PDE machines

Analogic cellular PDE machines

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international Joint conference on Neural Networks (IJCNN)

作者： C. Rekeczky I. Szatmari P. Foldesy T. Roska Computer and Automation Research Institute Hungary Hungarian Academy of Science Budapest Hungary Jedlik Laboratories Department of Information Technology Pázmány Péter Catholic University Budapest Hungary

this paper gives an overview on analogic cellular array architectures that can also be used to approximate partial differential equations (PDEs). Cellular arrays are massively parallel computing structures composed of cells placed on a regular grid. these cells interact locally an th e array can have both local and global dynamics. the software of this architecture is an analogic algorithm that builds on analog and logical spatio-temporal instructions of the underlying hardware, that is a locally connected cellular nonlinear network (CNN). Within this framework two classes of PDEs, motivated also by image processing methodologies will be discussed: (i) reaction-diffusion (local) types and (ii) contrast modification (global) types. It will be shown that based on cellular diffusion and wave-computing formulations these classes can be approximated on existing CNN Universal Machine (CNN-UM) chips. thus, the last generation of stored program topographic array microprocessors with integrated sensing and computing could also be viewed as the first prototypes of analogic cellular PDE machines implemented on silicon.

关键词： Computer architecture Cellular neural networks Partial differential equations parallel processing Software algorithms Hardware Cellular networks Image processing Turing machines Microprocessors

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Low-power high-order band-pass active-RC allpole filters using a "lossy" LP-BP transformation

Low-power high-order band-pass active-RC allpole filters usi...

引用

IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： D. Jurisic N. Mijat G.S. Moschytz Department of Electronic Systems and Information Processing University of Zagreb Zagreb Croatia Signal and Information Processing Laboratory (ISI) Swiss Federal Institute of Technology Zurich Switzerland

the design procedure for high-order single amplifier BP filters is presented. A method for the design of 2/sup nd/- and 4/sup th/-order band-pass (BP) active-RC filters using a modified low-pass to band-pass (LP-BP) frequency transformation, has already been presented in previous works. It showed that a BP filter could be realized simply by the substitution of resistors and capacitors of the ladder in a low-pass (LP) prototype filter, by serial and parallel RC circuits. Such a substitution results from a so-called "lossy" LP-BP transformation. In this paper, the design procedure is extended to higher-order BP filters, such as 6th- and 8th-order. the design procedure is simple, and the closed-form design equations are presented. Furthermore, it is shown that "impedance tapering" decreases sensitivities to component tolerances for the LP prototype, as well as for the resulting BP filter. Schoeffler's sensitivity measure is used for the sensitivity analysis.

关键词： Band pass filters Prototypes Design methodology Frequency Resistors Capacitors Low pass filters Circuits Equations Impedance

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A high effective algorithm of 32-bit multiply and MAC instructions' VLSI implementation with 32/spl times/8 multiplier-accumulator in DSP applications

A high effective algorithm of 32-bit multiply and MAC instru...

引用

international conference on Signal processing Proceedings (ICSP)

作者： Ze Tian Dun-shan Yu Yu-lin Qiu Microelectron. R&D Center Acad. Sinica Beijing China Institute of Microelectronics Peking University Beijing China Microelectronics R&D Center of Chinese Academy of Sciences Beijing China

ISBN: (纸本)0780374886

Multiply and multiply-accumulate (MAC) instructions (see ARM DDI0l00E, ARM Architecture Reference Manual) are fundamental instructions in DSP applications. In an embedded digital signal processing (DSP) core and high-performance enhanced DSP instruction processor core, the implementation of high-performance multiply and MAC instructions is very important. An algorithm of 32/spl times/32 multiply and MAC instructions' VLSI implementation with 32/spl times/8 multiplier-accumulator in DSP applications is presented. the 32/spl times/32 multiplication is achieved by 4 times 32/spl times/8 multiplication. the result of one 32/spl times/8 multiplication serves as a partial product of the next 32/spl times/8 operation; when the result of four such multiplications is accumulated, we get the result of 32/spl times/32. the 32/spl times/8 multiplication is only implemented by the hardware Booth multiplier. the algorithm of multiply and MAC instructions' implementation is the better trade-off between serial multiplier and parallel multiplier.

关键词： Very large scale integration Digital signal processing Signal processing algorithms Hardware Clocks Silicon Microelectronics Embedded system Research and development Speech processing

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VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding

VLSI-based parallel architecture for block-matching motion e...

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8th IEEE international conference on Electronics, Circuits and Systems

作者： Xu, DL Bentley, J Univ Teesside Sch Sci & Technol Middlesbrough TS1 3BA Cleveland England

ISBN: (纸本)0780370570

In this paper, we proposed a flexible VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.

关键词： parallel architectures

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Optimal parallel algorithms for cut vertices, bridges, and Hamiltonian Path in bounded interval tolerance graphs

Optimal parallel algorithms for cut vertices, bridges, and H...

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8th international conference on parallel and Distributed Systems (ICPADS 2001)

作者： Adhar, GS Univ N Carolina Dept Comp Sci Wilmington NC 28403 USA

ISBN: (纸本)0769511538

We present parallel algorithms to find cut vertices, bridges, and Hamiltonian Path in bounded interval tolerance graphs. For a graph with n vertices, the algorithms require O (log n) time and use O (n) processors to run OR. Concurrent Read Exclusive Write parallel RAM (CREW PRAM) model of computation. Our approach transforms the original graph problem to a problem in computational geometry. the total work done by the parallel algorithms is comparable to the work done by the best known sequential algorithms for the more restricted class of graphs, namely, interval graphs and permutation graphs. In this sense our algorithms have optimal complementary.

关键词： parallel algorithms

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Adaptive parallel Distributive Join algorithm for skewed data

Adaptive parallel Distributive Join algorithm for skewed dat...

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8th international conference on parallel and Distributed Systems (ICPADS 2001)

作者： Chung, SM Chatterjee, A Wright State Univ Dept Comp Sci & Engn Dayton OH 45435 USA

ISBN: (纸本)0769511538

In this paper, we present an adaptive version of the parallel Distributive Join (DJ) algorithm that we proposed in [1]. the adaptive parallel DJ algorithm can handle the data skew in operand relations efficiently. We implemented the original and adaptive parallel DJ algorithms on a network of Alpha workstations using the parallel Virtual Machine (PVM). We analyzed the performance of the algorithms, and compared it with that of the parallel Hybrid-Hash (KH) join algorithms. Our results show that the parallel DJ algorithms perform comparably with the parallel HH join algorithms over the entire range of the number of processors used and for different join selectivities. A significant advantage of the parallel DJ algorithms is that they can easily support non-equijoin operations.

关键词： parallel algorithms

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Performance of parallel I/O scheduling strategies on a network of workstations

Performance of parallel I/O scheduling strategies on a netwo...

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8th international conference on parallel and Distributed Systems (ICPADS 2001)

作者： Chen, FY Majumdar, S Carleton Univ Dept Syst & Comp Engn Ottawa ON K1S 5B6 Canada

ISBN: (纸本)0769511538

Techniques for scheduling parallel I/O for both uniprogrammed systems that run single jobs in isolation and multiprogrammed environments that execute multiple parallel jobs simultaneously ate presented. the performance of the scheduling algorithms is evaluated on a network of workstations. A new scheduling algorithm proposed in this paper is observed to perform very well for systems running single jobs in isolation. the algorithms that use knowledge of job characteristics are observed to produce a superior performance in multiprogrammed parallel environments.

关键词： parallel processing systems

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