In data intensive applications, bothprogramming and declarative query languages have attractions, the former in comprehensiveness and the latter for ease of use. Databases sometimes support the calling of side-effect ...
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the proceedings contain 70 papers. the special focus in this conference is on High Performance Computing. the topics include: High-performance computing and visualization;2-d wavelet transform enhancement on general-p...
ISBN:
(纸本)3540003037
the proceedings contain 70 papers. the special focus in this conference is on High Performance Computing. the topics include: High-performance computing and visualization;2-d wavelet transform enhancement on general-purpose microprocessors;a general data layout for distributed consistency in data parallel applications;duplication-based scheduling algorithm for interconnection-constrained distributed memory machines;evaluating arithmetic expressions using tree contraction;a mechanism to reduce i-cache power consumption in high performance microprocessors;exploiting web document structure to improve storage management in proxy caches;high performance multiprocessor architecture design methodology for application-specific embedded systems;a low latency messaging infrastructure for Linux clusters;low-power high-performance adaptive computing architectures for multimedia processing;a technique to construct high performance CORBA applications;automatic search for performance problems in parallel and distributed programs by using multi-experiment analysis;an adaptive value-based scheduler and its RT-Linux implementation;effective selection of partition sizes for moldable scheduling of parallel jobs;runtime support for multigrain and multiparadigm parallelism;a fully compliant openMP implementation on software distributed shared memory;a fast connection-time redirection mechanism for internet application scalability;an efficient resource sharing scheme for dependable real-time communication in multihop networks;improving web server performance by network aware data buffering and caching;wraps scheduling and its efficient implementation on network processors;performance comparison of pipelined hash joins on workstation clusters and iterative algorithms on heterogeneous network computing.
Software radio becomes one of the central themes of wireless communications this decade. As the complexity of computations and system requirements of the software radio go beyond the capabilities of current technologi...
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Software radio becomes one of the central themes of wireless communications this decade. As the complexity of computations and system requirements of the software radio go beyond the capabilities of current technologies, we identify major technology, development and research issues and the possible approach to its gradual implementation. We present our approach to the software radio implementation and describe a scenario for experimenting with various concepts that will be integrated in software radio. We discuss underlying system architectures, system design tools and their hierarchy, design flow and describe the platform and design flow used in our experiments.
this paper presents a design procedure for an HDTV encoder withparallelprocessing architecture, which could get out the dilemma lying in high-speed digital processing circuitry and real-time compression. In the prop...
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ISBN:
(纸本)0780375106
this paper presents a design procedure for an HDTV encoder withparallelprocessing architecture, which could get out the dilemma lying in high-speed digital processing circuitry and real-time compression. In the proposed system, an original HDTV picture is split to multiple sub-pictures of MPEG-2 MP@ML level, and then multiple sub-picture encoding modules (SEM) perform, respectively and simultaneously, MPEG-2 coding in the light of a joint rate control scheme. A normative HDTV PES stream of MPEG-2 MP@HL is built up by compositing multiple ES streams with different bit-rate. the paper hits the high points and supply appropriate implementation strategy during the propose design framework.
Transmission electron microscopy (TEM) and microhardness indentation techniques have been used to examine the microstructural evolution and age hardening behaviour of two Al-Cu-Mg alloys containing 1.1 atomic percent ...
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Transmission electron microscopy (TEM) and microhardness indentation techniques have been used to examine the microstructural evolution and age hardening behaviour of two Al-Cu-Mg alloys containing 1.1 atomic percent Cu and up to 0.5 atomic percent Mg. Carefully controlled ageing treatments followed the schedule of: solution treatment (525degreesC) + water quench (23degreesC) + (a) artificial ageing (150degreesC) or (b) natural ageing (up to 24 h at 23degreesC) + artificial ageing (150degreesC). the implementation of a natural ageing step at 23degreesC following quenching significantly influences the characteristics of precipitate nucleation and growth, resulting in (1) a more uniform precipitate distribution and (2) the clearly increased incidence of an additional precipitate phase (possibly Omega) residing parallel to {111}(alpha) matrix planes and in association with former dislocation loops.
A high-speed matched filter for searching synchronization in direct sequence spread spectrum (DSSS) receiver is studied. A model to implement the matched filter by hardware description languages (HDL) is proposed. the...
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ISBN:
(纸本)0780375106
A high-speed matched filter for searching synchronization in direct sequence spread spectrum (DSSS) receiver is studied. A model to implement the matched filter by hardware description languages (HDL) is proposed. the proposed model is based on parallelprocessing and pipeline architecture including circular buffer, multiplier, adder, and code look-up table. the proposed model is analyzed with respect to the performance and compared with a conventional digital signal processor (DSP) implementation.
High-Speed Transport mechanisms are becoming increasingly important as the demand for high bandwidth continues to grow. A number of High-Speed networks are evolved through various transport techniques like Plesiochron...
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High-Speed Transport mechanisms are becoming increasingly important as the demand for high bandwidth continues to grow. A number of High-Speed networks are evolved through various transport techniques like Plesiochronous Digital Hierarchy (PDH), Synchronous Digital Hierarchy (SDH), Dense Wavelength Division Multiplexing (DWDM) and Digital Wrappers. With complex architectures, synchronization of these networks becomes quite a challenging task. this paper discusses evolution of digital networks and synchronization architectures. the international Telecommunication Union (ITU) recommendation for SDH Equipment Slave Clocks (SEC) timing specification is G.813. the paper also covers implementations of SDH Equipment Slave Clocks and their timing characteristics.
In this paper, the discrete state space recursive filters are implemented in the form of parallel array processors. the state space description permits the straightforward application of systolic architectures to real...
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In this paper, the discrete state space recursive filters are implemented in the form of parallel array processors. the state space description permits the straightforward application of systolic architectures to realize recursive filters of 1D and 2D types. We show that the recursivity inherent to the filtering algorithm introduces a latency proportional to the filter order. Moreover, we show that the use of the CTP decomposition technique together withthe cylindrical-type structures reduces significantly this latency and improves the computation throughput of these arrays. the processing cells of the systolic array are designed via switched-capacitor techniques.
In this paper, a pipeline architecture supporting both8 /spl times/ 8 discrete cosine transform (DCT) and its inverse is described. A regular two-dimensional algorithm with perfect shuffle topology for DCT is derived...
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In this paper, a pipeline architecture supporting both8 /spl times/ 8 discrete cosine transform (DCT) and its inverse is described. A regular two-dimensional algorithm with perfect shuffle topology for DCT is derived. the resulting signal flow graph is mapped vertically onto sequential processing units. A similar pipeline architecture is derived for the inverse transform. the unified architecture is obtained by mapping both previous pipelines onto common resources. the proposed architecture contains three multipliers for 8 /spl times/ 8 transforms and its throughput can be increased with additional pipelining.
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