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检索条件"任意字段=8th International Conference on Algorithms and Architectures for Parallel Processing"
2885 条 记 录,以下是2451-2460 订阅
A parallel computation of power system equations  7
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7th European conference on parallel Computing, Euro-Par 2001
作者: Fung, Y.F. Ercan, M.F. Ho, T.K. Cheung, W.L. Dept. of Electrical Eng The Hong Kong Polytechnic University Hong Kong School of Electrical and Electronic Eng Singapore Polytechnic Singapore
Streaming SIMD Extensions (SSE) is a unique feature embedded in the Pentium III and P4 classes of microprocessors. By fully exploiting SSE, parallel algorithms can be implemented on a standard personal computer and a ... 详细信息
来源: 评论
parallel tree projection algorithm for sequence mining  7
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7th European conference on parallel Computing, Euro-Par 2001
作者: Guralnik, Valerie Garg, Nivea Karypis, George University of Minnesota Department of Computer Science and Engineeering/Army HPC Research Center MinneapolisMN United States
Discovery of sequential patterns is becoming increasingly useful and essential in many scientific and commercial domains. Enormous sizes of available datasets and possibly large number of mined patterns demand efficie... 详细信息
来源: 评论
A scheduling mechanism for lock-free operation of a lightweight process library for SMP computers
A scheduling mechanism for lock-free operation of a lightwei...
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8th international conference on parallel and Distributed Systems
作者: Oguma, H. Nakayama, Y. Department of Computer Science The Univ. of Electro-Communications Chofu Tokyo 182-8585 Japan
We have designed and implemented a lightweight process (thread) library called "Lesser Bear" for SMP computers. Lesser Bear has high portability and thread-level parallelism. Lesser Bear executes threads in ... 详细信息
来源: 评论
An area-efficient interpolation filter using block structure
An area-efficient interpolation filter using block structure
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IEEE international conference on Electronics, Circuits and Systems (ICECS)
作者: Kyu Ha Lee Dae Hee Youn Chungyong lee Research & Development Team Samsung Thales Company Limited Suwon Kyunggi South Korea Department of Electrical and Electronic Engineering Yonsei University Seoul South Korea
A new interpolation filtering architecture using block structure and look-up table (LUT) is proposed. Using parallel processing inherited from block structure, the filtering rate and the power consumption are lowered,... 详细信息
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A reconfigurable 2D convolver for real-time SAR imaging
A reconfigurable 2D convolver for real-time SAR imaging
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IEEE international conference on Electronics, Circuits and Systems (ICECS)
作者: A.G.M. Strollo E. Napoli D. De Caro G.P. Saggese Department of Electronics and Telecommunications Engineering University of Naples Napoli Italy
A novel architecture for real-time synthetic aperture radar signal processing that achieves real-time processing by using a recently proposed signum coded algorithm and time domain processing, is presented. New archit... 详细信息
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Scanning biosequence databases on a hybrid parallel architecture  7
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7th European conference on parallel Computing, Euro-Par 2001
作者: Schmidt, Bertil Schröder, Heiko Schimmler, Manfred School of Computer Engineering Nanyang Technological University 639798 Singapore Institut für Datenverarbeitungsanlagen TU Braunschweig Hans-Sommer-Str. 66 Braunschweig38106 Germany
Molecular biologists frequently scan sequence databases to detect functional similarities between proteins. Even though efficient dynamic programming algorithms exist for the problem, the required scanning time is sti... 详细信息
来源: 评论
A framework for a wavelet-based high level environment
A framework for a wavelet-based high level environment
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IEEE international conference on Electronics, Circuits and Systems (ICECS)
作者: M. Nibouche A. Bouridane O. Nibouche School of Computer Science Queen''s University Belfast Belfast UK
Although FPGA technology offers the potential of designing high performance systems at low cost for a wide range of applications, its programming model is prohibitively low level requiring either a dedicated FPGA-expe... 详细信息
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the low power baseband processing parts of a novel dual mode DECT/GSM terminal
The low power baseband processing parts of a novel dual mode...
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IEEE international conference on Electronics, Circuits and Systems (ICECS)
作者: C. Drosos C. Dre D. Metafas D. Soudris S. Blionas Intracom S.A. Hellenic Telecommunications and Electronics Industry Paiania Greece Department of Electrical & Computer Engineering Xanthi Greece
In order to support a dual mode DECT/GSM terminal architecture, with low power characteristics and integrated support for direct conversion terminal architecture the basic parts of such a terminal were designed and im... 详细信息
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Memory hierarchy layer assignment for data re-use exploitation in multimedia algorithms realized on predefined processor architectures
Memory hierarchy layer assignment for data re-use exploitati...
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IEEE international conference on Electronics, Circuits and Systems (ICECS)
作者: K. Masselos F. Catthoor A. Kakarudas C.E. Goutis H. De Man VLSI Design Laboratory Department of Electrical and Computer Engineering University of Patras Rio Greece IMEC Leuven Belgium Department of Katholieke Univ Leuven Belgium
A systematic approach for the assignment of array type data structures to the layers of fixed memory hierarchies present in instruction set processors is presented. Memory Hierarchy Layer Assignment (MHLA) is required... 详细信息
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Realization of an airborne radar parallel signal processing system
Realization of an airborne radar parallel signal processing ...
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IEEE international conference on Radar
作者: Xu Junyi Wang Xiutan Peng Yingning Department of Electronic Engineering Tsinghua University Beijing China
In order to fulfil real time signal processing tasks such as clutter rejection, moving target detection (MTD) and constant false alarm rate (CFAR) control in airborne radar, an airborne radar parallel signal processin... 详细信息
来源: 评论