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Multi-window recursive adaptive neural filters

Multi-window recursive adaptive neural filters

引用

IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： A. Burian J. Saarinen P. Kuosmanen Digital Media Institute Tampere University of Technology Tampere Finland

Generalized adaptive neural filters are a class of nonlinear adaptive filters that includes stack filters as a subset. We further extend this class by using a multi-window approach. In this way we obtain a parallel recursive filtering operation and make better use of the implicit parallelism of the neural network architecture. the proposed neural network structure uses shared weight architecture for efficient implementation. Experimental results in actual image processing illustrate the efficiency of the approach.

关键词： Adaptive filters Neural networks Convergence Signal analysis Filtering Image processing Nonlinear filters Electronic mail Smoothing methods Statistics

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JPEG 2000: finite precision representation and hardware implications

JPEG 2000: finite precision representation and hardware impl...

引用

IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： M. Martina G. Masera G. Piccinini F. Vacca M. Zamboni Dipartimento di Elettronica Politecnico di Torino Torino Italy

In many signal processing applications, widely used in new multimedia based systems, finite precision representation effects are of great concern. When hardware platform are involved, such for VLSI designs, these problems are particularly important, in order to obtain high performance, compact and power-conscious architectures. In particular fixed point effects have not yet been emphasized enough for the forthcoming standard JPEG 2000. In this paper a detailed study of quantization noise effects and their hardware impact is presented. the final objective is to investigate the possibility to exploit finite precision data representation in order to design low cost and low power systems.

关键词： Hardware Discrete wavelet transforms Filter bank Very large scale integration Polynomials Encoding Electronic mail Signal processing Multimedia systems Quantization

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Fast 32-bit digital multiplier

Fast 32-bit digital multiplier

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： K. Raahemifar M. Ahmadi Electrical & Computer Engineering Department Ryerson Polytechnic University Toronto ONT Canada Electrical Engineering Department University of Windsor Windsor ONT Canada

this paper presents a high-speed VLSI implementation structure for a multiplier. Four n-bit numbers are generated using even and odd positions of the two n-bit numbers. then they are multiplied pairwise. A parallel addition algorithm is used to add up the partial products. three k-bit numbers at each level are converted to two (k+1)-bit numbers at the next level using a 3-to-2 adding technique. Carry propagation is left to the last stage of multiplier where a fast carry-look-ahead adder is used to add the final two 2(n-1)-bit numbers. the supply voltage (V/sub dd/) is 3.3 /spl upsi/ which can be lowered to 2.5 /spl upsi/. the multiplier are in 0.8 /spl mu/m technology. HSPICE simulation shows a total delay of 3.25 ns for a 32-bit multiplier.

关键词： Delay Signal processing algorithms Very large scale integration Adders Computer applications Application software CMOS technology Ash Voltage Computational modeling

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FPGA based on-line complex-number multipliers

FPGA based on-line complex-number multipliers

引用

IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： A. Perez-Pascual T. Sansaloni J. Valls Dpto Ingeniería Electrónica Universidad Politécnica de Valencia Gandia Spain

this paper proposes two topologies of radix-2 complex-number multipliers based on distributed arithmetic and the redundant signed-digit representation. the advantage of this approach is twofold: the distributed arithmetic reduces the hardware requirements respect to direct implementation of the complex-number multiplication, and the redundant number system avoids the carry-propagation and allows computing on-line the digits. Two Radix-2 architectures are presented. these multipliers have been implemented on FPGA and an optimum mapping is proposed. the presented circuits have been compared to other complex-number multipliers leading to more efficient area-time structures and a lower latency.

关键词： Field programmable gate arrays Arithmetic Digital signal processing Chromium Delay Table lookup Computer architecture Logic OFDM throughput

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A massively parallel architecture for linear machine code genetic programming 4th

A massively parallel architecture for linear machine code ge...

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4th international conference on Evolvable Systems: From Biology to Hardware, ICES 2001

作者： Eklund, Sven E. Dalama University Sweden

ISBN: (纸本)354042671X

Over the last decades Genetic algorithms (GA) and Genetic Programming (GP) have proven to be efficient tools for a wide range of applications. However, in order to solve human-competitive problems they require large amounts of computational power, particularly during fitness calculations. In this paper I propose the implementation of a massively parallel model in hardware in order to speed up GP. this fme-grained diffusion architecture has the advantage over the popular Island model of being VLSI-friendly and is therefore small and portable, without sacrificing scalability and effectiveness. the diffusion architecture consists of a large amount of independent processing nodes, connected through an X-net topology, that evolve a large number of small, overlapping sub-populations. Every node has its own embedded CPU, which executes a linear machine code representation of the individuals. Preliminary simulation results (low-level VHDL simulation) indicate a performance of 10.000 generations per second (depending on the application). One node requires 10-20.000 gates including the CPU (also application dependent), which makes it possible to fit up to 2.000 individuals in one FPGA (Virtex XC2V10000). © Springer-Verlag Berlin Heidelberg 2001.

关键词： Genetic programming

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High data rate synchronizers operating at low speed

High data rate synchronizers operating at low speed

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： A.D. Reis J.F. Rocha A.S. Gameiro J.P. Carvalho Dep. de Electrónica e Telecomunicações Universidade de Aveiro UA Aveiro Portugal Dep. de Fisica Universidade da Beira Interior Covilhã UBI Covilhã Portugal

this paper presents a new technique which allows high baud rate with low operation speed of the synchronizer. this technique is based on parallel processing. What is done by only one clock operating at the baud rate can be done by two clocks operating only at half rate. By generalizing we propose versions of clock recovery circuits operating at the ratio 1/2/sup n/ of the data rate. thus we obtain circuits transmitting at very high data rate but operating at very low frequency. the proposed circuits which are transition sensitive (digital) are compared with the traditional level sensitive (analog).

关键词： Clocks Voltage-controlled oscillators Frequency synchronization Flip-flops Pulse circuits Telecommunications parallel processing Multiplexing Delay Pulse generation

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Distributed evolutionary design of constant-coefficient multipliers

Distributed evolutionary design of constant-coefficient mult...

引用

IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： D. Chen T. Aoki N. Homma T. Higuchi Higuchi Laboratory Graduate School of Information Sciences University of Tohoku Sendai Japan

A parallel version of the evolutionary graph generation (EGG) system, called the distributed EGG (DEGG) system, was developed on a cluster of PCs using a message-passing interface (MPI). To demonstrate the capability of DEGG, it is applied to seeking the optimal design of various multipliers. Experimental results substantially show that DEGG consistently performs better than the EGG and known conventional designs.

关键词： Circuits Personal communication networks Digital signal processing Data flow computing Genetic mutations Laboratories Signal design Digital arithmetic Process design Design optimization

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An agent-based implementation of irregular pyramid for distributed image segmentation

An agent-based implementation of irregular pyramid for distr...

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international conference on Emerging Technologies and Factory Automation (ETFA)

作者： E. Duchesnay J.-J. Montois Y. Jacquelet A. Kinie LTSI/GRAID Université de Rennes Saint Malo France

ISBN: (纸本)0780372417

We propose a solution to handle two problems inducted by the growth of the complexity of machine vision systems: (1) the need of a robust, open and flexible framework to control various descriptive and operational knowledge; and (2) the necessity to have an architecture which offer parallel processing that can be easily scaled to an evolving underlying hardware. We propose an agent society, implemented in the Java language, that is organized as an irregular pyramid for many reasons: (1) an agent provides an abstraction to encapsulate reactive or cognitive processing; and (2) the pyramid proposes a formal graph-based approach to ensure global and distributed goal satisfaction. the evaluation of the architecture performed on a X-scanner breast image, shows good quality results and parallel processing abilities.

关键词： Image segmentation Machine vision Hardware parallel processing Muscles Control systems Breast Computer architecture Computer vision Microcomputers

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A parallel 3D DCT architecture for the compression of integral 3D images

A parallel 3D DCT architecture for the compression of integr...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： A. Aggoun I. Jalloh 3D Imaging Technologies Group Faculty of Computing Sciences and Engineering De Montfort University Leicester UK

A new VLSI architecture for the computation of the three-dimensional discrete cosine transform (3D DCT) for compression of integral 3D images is proposed. the 3D DCT is decomposed into 1D DCTs computed in each of the three dimensions. the architecture is a parallel structure which computes an N/spl times/N/spl times/N-point DCT by computing N N/spl times/N 2D DCTs in parallel and feeding each of the computed 2D DCT coefficients into a final ID DCT block. the architecture uses 5N/sup 2//2 multiplier-accumulators to evaluate N/spl times/N/spl times/N-point DCT's at a rate of N complete 3D DCT coefficients per clock cycles, where N is even. the architecture is regular and modular and as such it is suitable for VLSI implementation. the proposed architecture has a better area-time performance than previously reported 3D DCT architectures. Also, the proposed architecture reduces the initial delay by a factor of N.

关键词： Discrete cosine transforms Image coding Computer architecture Lenses Microoptics Very large scale integration Concurrent computing Optical imaging Assembly Delay

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A sampled-analog rank-order-filter architecture

A sampled-analog rank-order-filter architecture

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： U. Cilingiroglu L.E. Dake Electrical Engineering Department Texas A and M University College Station TX USA Texas Instruments Inc. Dallas TX USA

We propose a sampled-analog rank-order filter (ROF) architecture of complexity O(n/sup 2/). It yields a very compact structure because the devices used are essentially of minimum geometry. Its sole active building block being the simple CMOS inverter, the circuit exhibits an excellent low-voltage compatibility. Furthermore, it can support a rail-to-rail input range. It is inherently fast due to the fully parallel signal processing, and the speed is expected to increase with technological scaling at the same rate as purely digital circuitry. Finally, it supports full programmability of the rank by means of an analog reference voltage. the ROF is based on a pair of multiple-winners-take-all (mWTA) circuits and a set of AND gates. the paper includes a description of the architecture and a detailed analysis of the mWTA. Most relevant design issues are addressed, and experimental results obtained from a fabricated ROF are presented.

关键词： Inverters Circuits Nonlinear filters Voltage Clocks Signal processing Capacitors Virtual reality Biomedical signal processing Application software

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