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Towards run-time actor mapping of dynamic dataflow programs onto multi-core platforms

Towards run-time actor mapping of dynamic dataflow programs ...

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international Symposium on Image and Signal processing and Analysis

作者： Hervé Yviquel Emmanuel Casseau Mickaël Raulet Pekka Jääskeläinen Jarmo Takala Inria IRISA France INSA of Rennes IETR France Tampere University of Technology Finland

the emergence of massively parallel architectures, along with the necessity of new parallel programming models, has revived the interest on dataflow programming due to its ability to express concurrency. Although dynamic dataflow programming can be considered as a flexible approach for the development of scalable applications, there are still some open problems in concern of their execution. In this paper, we propose a low-cost mapping methodology to map dynamic dataflow programs over any multi-core platform. Our approach finds interesting mapping solutions in few milliseconds that makes it doable at regular time by translating it in an equivalent graph partitioning problem. Consequently, a good load balancing over the targeted platform can be maintained even with such unpredictable applications. We conduct experiments across three MPEG video decoders, including one based on the new High Efficiency Video Coding standard. those dataflow-based video decoders are executed on two different platform: A desktop multi-core processor, and an embedded platform composed of interconnected and tiny Very Long Instruction Word - style processors. Our entire design flow is based on open-source tools. We present the influence of the number of processors on the performance and show that our method obtains a maximum decoding rate for 16 processors.

关键词： Program processors Decoding Streaming media Transform coding Multicore processing Video coding Dynamic scheduling

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Performance Optimization and Analysis of the Unstructured Discontinuous Galerkin Solver on Multi-Core and Many-Core architectures

Performance Optimization and Analysis of the Unstructured Di...

引用

IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Zhe Dai Liang Deng Yueqing Wang Fang Wang Ming Li Jian Zhang China Aerodynamics Research and Development Center Computational Aerodynamics Institute Mianyang China State Key Laboratory of Aerodynamics China Aerodynamics Research and Development Center Mianyang China

the discontinuous Galerkin (DG) algorithm is a representative high order method in Computational Fluid Dynamics (CFD) area which possesses considerable mathematical advantages such as high resolution, low dissipation, and dispersion. However, DG is rather computationally intensive to demonstrate practical engineering problems. this paper discusses the implementation of our in-house practical DG application in three different programming models, as well as some optimization techniques, including grid renumbering and mixed precision to maximize the performance improvements in a single node system. the experiment on CPU and GPU shows that our CUDA, OpenACC, and OpenMP-based code obtains a maximum speedup of 42.9x, 35.3x, and 8.1x compared with serial execution by the original application, respectively. Besides, we systematically compare the programming models in two aspects: performance and productivity. Our empirical conclusions facilitate the programmers to select the right platform with a suitable programming model according to their target applications.

关键词： Productivity Computational fluid dynamics Heuristic algorithms Graphics processing units Computer architecture Programming Mathematical models

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Architecture and implementation of the access mechanism for a bus-structured multiservice LAN

Architecture and implementation of the access mechanism for ...

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international conference on Distributed Computing Systems

作者： V. Pallios T. Antonakopoulos V. Makios Laboratory of Electromagnetics University of Patras Patras Greece

the design and implementation of a high-speed access mechanism for a fiber-optic multiservice LAN is presented. the handling of stream-type and burst-type communications is accomplished through the use of a distributed hybrid switching protocol that uses an asynchronous dynamic time-division-multiplexing technique. the network comprises a write channel in which each network node transmits and a read channel where the transmitted information is duplicated and thus received by the network nodes. In parallel with the write channel, a sense channel is responsible for detecting the right of access for the node. the protocol provides bounded delay for the packet-switched traffic and small buffering memory for the circuit-switched traffic, which together with the network bit rate and the node processing time and capacity set the network efficiency. Experimental results are presented for the node processing time and the network speed.< >

关键词： Local area networks Access protocols Packet switching Telecommunication traffic Circuits Optical fibers Optical buffering Optical packet switching Optical signal processing Bandwidth

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System-on-Chip Design with Dataflow Architecture

System-on-Chip Design with Dataflow Architecture

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the 8th international conference on Computer Supported Cooperative Work in Design(第八届计算机支持的协同工作设计国际会议)(CSCWD2004)

作者： Baifeng Wu Chenglian Peng Fudan University Shanghai 200433P.R.China

ISBN: (纸本)0780379411

this paper presents a practical approach toimplement data flow dominated System-on-Chip systemwith real-time requirements. With data flow model and avirtual component (VC)-oriented implementationarchitecture, the approach has the advantages ofeffectively supporting design reuse or *** bus architecture reduces the design complexityand implementation cost and provides an effective waysto meet real-time constraints. Based on the architecturesome important aspects such as bus arbitrating, VCframework are described, these techniques are criticalfactors for achieving design goal.

关键词： data flow graphs system-on-chip integrated circuit design parallel architectures microprocessor chips real-time systems system-on-chip design dataflow architecture real-time requirements dataflow model a virtual component-oriented implementation architecture design reuse design reconfiguration single bus architecture design complexity real-time constraints bus arbitration

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Pipeline architecture for two-dimensional discrete cosine transform and its inverse

Pipeline architecture for two-dimensional discrete cosine tr...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： J. Takala J. Nikara K. Punkka Institute of Digital and Computer Systems Tampere University of Technology Tampere Finland

In this paper, a pipeline architecture supporting both 8 /spl times/ 8 discrete cosine transform (DCT) and its inverse is described. A regular two-dimensional algorithm with perfect shuffle topology for DCT is derived. the resulting signal flow graph is mapped vertically onto sequential processing units. A similar pipeline architecture is derived for the inverse transform. the unified architecture is obtained by mapping both previous pipelines onto common resources. the proposed architecture contains three multipliers for 8 /spl times/ 8 transforms and its throughput can be increased with additional pipelining.

关键词： Discrete cosine transforms Pipeline processing Computer architecture Arithmetic Discrete transforms Topology throughput Video compression Signal processing parallel architectures

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An Efficient parallel CNN Inference Framework for Multi-zone Processor

An Efficient Parallel CNN Inference Framework for Multi-zone...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Jie Chen Zhong Liu College of Computer National University of Defense Technology Changsha China

Deep convolutional neural networks have been widely used in various fields, and how to accelerate and optimize the performance of neural network models according to the architectural characteristics of accelerator hardware has become the research hot spot. We propose and design an efficient parallel convolutional neural network inference framework named PCIF for multi-zone processor. Its core is a multi-core parallel and vectorized C++ operator library. PCIF has designed optimized data layout and transmission strategies, layer fusion and multi-image fusion methods, which can automatically parse and efficiently map existing neural network models to multi-core vector accelerators to accelerate inference computation. Users can also build new neural network models through the C++ and Python APIs provided by PCIF to achieve high performance inference computing. the results of the experiment show that the AlexNet, VGG-16, GoogleNet, and ResNet-50 network models achieve efficient computing performance using PCIF.

关键词： Quantization (signal) Multicore processing Computational modeling Neural networks C++ languages parallel processing Libraries

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Understanding the Architectural Characteristics of EDA algorithms

Understanding the Architectural Characteristics of EDA Algor...

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international conference on parallel processing (ICPP)

作者： Xin Wang Xiaofeng Ji Yunping Lu Yi Li Weijia Zhou Weihua Zhang Wenyun Zhao Parallel Processing Institute Fudan University Shanghai China School of Computer Science Fudan University Shanghai China

ISBN: (纸本)9781509028245

Currently, the release of different chip products has come to a burst. Time-to-market period of these products has been shortened to an extreme, nearly 8 to 12 months. To reduce production period, hardware architects try to shorten every design and manufacture stage. therefore, it has become one of the major concerns for them that how to accelerate electronic design automation (EDA) tools, which have been widely used throughout the lifetime of chip design and manufacture. While many prior efforts have done in-depth works on different acceleration techniques, such as IC-based, FPGA-based, or GPUbased, to our best knowledge, there has been no systematic study towards the architectural characteristics analysis for these EDA algorithms. this may impede the further optimizations and acceleration for them. In this paper, we make the first attempt to construct an EDA benchmark suite (EDAbench for short) for architectural design, parallel acceleration, and system optimization. EDAbench covers representative modern EDA algorithms. We then evaluate predominant architectural characteristics from three aspects including computation characteristics, memory hierarchy, and systematic characteristics. Experimental results reveal that there are some vital gaps between existing hardware and the requirements of EDA algorithms. Based on the analysis, we also give out some insights and propose suggestions for future optimization, acceleration, and architecture design.

关键词： Algorithm design and analysis Benchmark testing Optimization Acceleration Hardware Systematics Computer architecture

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A customized GPU acceleration of the princeton ocean model

A customized GPU acceleration of the princeton ocean model

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international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Shizhen Xu Xiaomeng Huang Yan Zhang Yong Hu Guangwen Yang Ministrv of Education Key Laboratory for Earth System Modeling Joint Center for Global Change Studies Beijing China

While GPU is becoming a compelling acceleration solution for a series of scientific applications, most existing work on climate models only achieved limited speedup. this is due to partial porting of the huge code and the memory bound inherence of these models. In this work, we design and implement a customized GPU-based acceleration of the Princeton Ocean Model (gpuPOM) based on mpiPOM, which is one of the parallel versions of the Princeton Ocean Model. Based on Nvidia's state-of-the-art GPU architectures (K20X and K40m), we rewrite the full mpiPOM model from the original Fortran version into the CUDA-C version. We present the GPU acceleration methods used in the gpuPOM, especially the techniques to ease its memory bound problem through better use of GPU's memory hierarchy. the experimental results indicate that the gpuPOM with one K40m GPU achieves from 6.3-fold to 16.7-fold speedup over different Intel multi-core CPUs and one K20X GPU achieves from 5.8-fold to 15.5-fold speedup.

关键词： Graphics processing units algorithms Meteorology Optimization Computational modeling Acceleration Instruction sets

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Impact of CUDA and OpenCL on parallel and Distributed Computing

Impact of CUDA and OpenCL on Parallel and Distributed Comput...

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international Conf on Electrical and Electronic Engineering (ICEEE)

作者： Abu Asaduzzaman Alec Trent S. Osborne C. Aldershof Fadi N. Sibai Wichita State University Wichita Kansas USA Prince Mohammad Bin Fahd University Al-Khobar Saudi Arabia

ISBN: (纸本)9781665440714;9781665411615

Along with high performance computer systems, the Application Programming Interface (API) used is crucial to develop efficient solutions for modern parallel and distributed computing. Compute Unified Device Architecture (CUDA) and Open Computing Language (OpenCL) are two popular APIs that allow General Purpose Graphics processing Unit (GPGPU, GPU for short) to accelerate processing in applications where they are supported. this paper presents a comparative study of OpenCL and CUDA and their impact on parallel and distributed computing. Mandelbrot set (represents complex numbers) generation, Marching Squares algorithm (represents embarrassingly parallelism), and Bitonic Sorting algorithm (represents distributed computing) are implemented using OpenCL (version 2.x) and CUDA (version 9.x) and run on a Linux-based High Performance Computing (HPC) system. the HPC system uses an Intel i7-9700k processor and an Nvidia GTX 1070 GPU card. Experimental results from 25 different tests using the Mandelbrot Set generation, the Marching Squares algorithm, and the Bitonic Sorting algorithm are analyzed. According to the experimental results, CUDA performs better than OpenCL (up to 7.34x speedup). However, in most cases, OpenCL performs at an acceptable rate (CUDA speedup is less than 2x).

关键词： Performance evaluation High performance computing Graphics processing units Computer architecture parallel processing Hardware Generators

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Adaptive parallel Interval Global Optimization algorithms Based on their Performance for Non-dedicated Multicore architectures

Adaptive Parallel Interval Global Optimization Algorithms Ba...

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Euromicro conference on parallel, Distributed and Network-Based processing

作者： J.F. Sanjuan Estrada L.G. Casado I. García Universidad de Almeria Almeria AndalucÃa ES Department of Computer Architecture and Electronics University of Almeria Almería Spain Department of Computer Architecture University of Mälaga Mälaga Spain

Branch and Bound (B&B) algorithms are highly parallelizable but they are irregular and dynamic load balancing techniques have been used to avoid idle processors. In previous work, authors use a dynamic number of threads at run time, which depends on the measured performance of the application for just one interval B&B algorithm running on the system. In this way, load balancing is achieved by thread generation decisions. In this work, we extend the study of these models to non-dedicated systems. In order to have a controlled test bed and comparable results, several instances of the interval global optimization algorithm are executed in the system, with the same model and problem to solve. therefore, a non-dedicated system is simulated because the execution of one application affects the execution of the other instances. this paper discusses different methods and models to decide when a thread should be created. Experiments show which of the proposed methods performs best in terms of maximum running time per application, using the fewest running threads. Following this parallel programming methodology, which is well suited for other B&B codes, applications can adapt their parallelism level to their performance and load of the system(at run time). this work represents a step forward towards increasing the performance of parallel algorithm running in non-dedicated and heterogeneous systems. the adaptive model discussed in this work is able to reduce the overall execution time for a set of instances of the same application running simultaneously. It also exempts the user from specifying the number of threads each application should use.

关键词： Instruction sets Kernel Computational modeling Adaptation model Load modeling parallel processing

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