this paper describes a single chip massively parallel special array processor which can be used as a new high performance accelerator for design error simulation. the new accelerator adopts simple logic element and co...
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this paper describes a single chip massively parallel special array processor which can be used as a new high performance accelerator for design error simulation. the new accelerator adopts simple logic element and communication interface with minimum transistors. Using this, high speed simulation can be performed.
the proceedings contain 38 papers. the special focus in this conference is on Fine Grain parallelism I and Interprocedural Analysis. the topics include: Array data flow analysis for load-store optimizations in supersc...
ISBN:
(纸本)9783540607656
the proceedings contain 38 papers. the special focus in this conference is on Fine Grain parallelism I and Interprocedural Analysis. the topics include: Array data flow analysis for load-store optimizations in superscalar architectures;an experimental study of an ILP-based exact solution method for software pipelining;an alternative to list scheduling for modulo schedulers;interprocedural array region analyses;interprocedural analysis for parallelization;interprocedural array data-flow analysis for cache coherence;an interprocedural parallelizing compiler and its support for memory hierarchy research;a calculus for the compilation of data parallel languages;transitive closure of infinite graphs and its applications;demand-driven, symbolic range propagation;optimizing fortran 90 shift operations on distributed-memory multicomputers;a loop parallelization algorithm for HPF compilers;fast address sequence generation for data-parallel programs using integer lattices;compiling array statements for efficient execution on distributed-memory machines;a communication backend for parallel language compilers;parallel simulation of data parallel programs;a parallelprocessing support library based on synchronized aggregate communication;a MATLAB interactive restructuring compiler;a simple mechanism for improving the accuracy and efficiency of instruction-level disambiguation;improving super-scalar processor performance;integer loop code generation for VLIW;piecewise execution of nested data-parallel programs;recovering logical structures of data;efficient distribution analysis via graph contraction;automatic selection of dynamic data partitioning schemes for distributed-memory multicomputers;data redistribution in an automatic data distribution tool and general purpose optimization technology.
the Micro-Grain Array Processor-2 (MGAP-2) is a two dimensional SIMD array of 49,152 fine-grain processors, designed primarily for high performance signal processing. Each processor can compute any one of 65,536 boole...
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the Micro-Grain Array Processor-2 (MGAP-2) is a two dimensional SIMD array of 49,152 fine-grain processors, designed primarily for high performance signal processing. Each processor can compute any one of 65,536 boolean transformations. What separates the MGAP-2 from existing fine-grain arrays is its processor level interconnect control. Each processor can independently select its communication direction. this allows a programmer to cluster groups of processors into larger computational units, and provides flexible interprocessor communication.
We present a single chip circuit solution to a concept called Near-Sensor Image processing, which includes image sensing, image processing and feature extraction. We give solutions to the three main implementation pro...
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We present a single chip circuit solution to a concept called Near-Sensor Image processing, which includes image sensing, image processing and feature extraction. We give solutions to the three main implementation problems. A small photodiode read-out unit, which is locally compensated for process variations, a low power processor element and an instruction line driver, suitable for massively parallel processors are described. A 16 × 16 elements prototype has been built. However most of the results come from simulations of an improved 128 × 128 matrix.
the proceedings contain 28 papers. the special focus in this conference is on Quantitative Evaluation of Computing and Communication Systems. the topics include: Evaluation of a CPU scheduling mechanism for synchroniz...
ISBN:
(纸本)9783540603009
the proceedings contain 28 papers. the special focus in this conference is on Quantitative Evaluation of Computing and Communication Systems. the topics include: Evaluation of a CPU scheduling mechanism for synchronized multimedia streams;a tool for performance evaluation of relational database programs;measuring fault tolerance withthe FTAPE fault injection tool;queueing analysis of discrete-time buffer systems with compound arrival process and variable service capacity;the method of moments for higher moments and the usefulness of formula manipulation systems;integration of performance evaluations in the design process of CPUs and computer systems;information requirements for software performance engineering;integrating behavioural and simulation modelling;assessment of 3rd generation mobile systems by simulation;on the exact and approximate analysis of hierarchical discrete time queueing networks;steady state analysis of markov regenerative SPN with age memory policy;a new iterative method for solving large-scale markov chains;a new iterative numerical solution algorithm for markovian queueing networks;transient analysis of deterministic and stochastic petri nets with timenet;QPN-tool for the specification and analysis of hierarchically combined queueing petri nets;a tool for analyzing causal relationships in parallel and distributed systems;a performance prediction tool;compile-time performance prediction of parallel systems;workload models for multiwindow distributed environments;building a hierarchical can-simulator and performance engineering of distributed software process architectures.
this paper presents a unique 2-stage pipeline PCM conference architecture, called NetConf, specially designed and realized as a single chip VLSI for processing PCM channels in order to provide conference in digital sw...
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this paper presents a unique 2-stage pipeline PCM conference architecture, called NetConf, specially designed and realized as a single chip VLSI for processing PCM channels in order to provide conference in digital switching systems. the NetConf conference circuit overcomes the manual handling of overflow problem, that exist in the current architectures, with a unique 2-stage pipelined architecture and a new AGC-Automatic Gain Control algorithm. the circuit can also provide regular connection and capable of doing 3 level attenuation, 4 level noise suppression on all or any selected channel. the circuit can be soft reseted and accept different frame synchronization timings. the conference circuit realized by European Silicon Structures' 0.7 micron CMOS technology and packaged in a 24 pin plastic DIL package. the die is 12 mm2 and consists of 12,000 gates including two four-ports static RAMs. this newly proposed 2-stage pipeline conference architecture provides better overflow and noise performance over existing architectures.
A customized image processor for real time convolution of an image has been developed. Image convolution requires an extensive amount of calculation capacity and I/O communication which is hard to sustain with standar...
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A customized image processor for real time convolution of an image has been developed. Image convolution requires an extensive amount of calculation capacity and I/O communication which is hard to sustain with standard processors in real time. therefore, a customized processor has been designed with a tailored architecture. the processors have a total sustained calculation capacity of > 2G arithmetic operations/s at 20MHz clock frequency, surpassing that of TMS320C80 for this application due to the tailored architecture.
the problem of bicriterion scheduling of jobs with identical processing times by uniform processors is considered. the first criterion is the minimization of either total or maximum costs, the second one is the minimi...
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the problem of bicriterion scheduling of jobs with identical processing times by uniform processors is considered. the first criterion is the minimization of either total or maximum costs, the second one is the minimization of maximum cost with different cost functions. Polynomial time algorithms are presented to determine all efficient solutions and the optimal solution for a given global criterion.
A low cost CCD camera system connected to a transputer network as a parallelprocessing device has been developed for the determination of human skin objects. Ultraviolet, visible and penetrative infrared images recor...
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the paper presents the design of a VLSI fuzzy processor which is capable ofperforming fuzzy inferences based on the -level sets theory. the use of the a-level sets family to represent fuzzy sets allows a considerable ...
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