the paper presents the design of a VLSI fuzzy processor which is capable ofperforming fuzzy inferences based on the -level sets theory. the use of the a-level sets family to represent fuzzy sets allows a considerable ...
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this paper describes a new method that uses the diffusion-like process to classify angles in a image. the proposed method exploits the curvature value of a contour line to characterize the correspondent angle. the eff...
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An important goal of a system's development team is to provide a software structure that evolves gracefully with its workload's intensity and characteristics, and the technologies that support the system. We d...
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Knowledge based systems (KBS) of first generation are characterized by the separation of domain specific knowledge and general problem solving strategies. Such systems lack of the following important abilities: knowle...
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Knowledge based systems (KBS) of first generation are characterized by the separation of domain specific knowledge and general problem solving strategies. Such systems lack of the following important abilities: knowledge acquisition according different paradigms of representation and processing, definition of deep knowledge caused by physiological processes of reasoning, and management of different abstraction levels. Next generation KBS provide a bases from managing these problems. Essential characteristics of this new systems are modularization of knowledge, distribution of knowledge across different hardware and software resources, and use of object-oriented technology for integrating symbolic and subsymbolic knowledge on different levels of abstraction.< >
A novel ceramic package for a two-chip silicon accelerometer and the signal conditioning ASIC chip assembly has been developed withthe advantage of being directly mounted on a PC board thus eliminating the need for a...
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A novel ceramic package for a two-chip silicon accelerometer and the signal conditioning ASIC chip assembly has been developed withthe advantage of being directly mounted on a PC board thus eliminating the need for additional mounting structures for automotive airbag applications. the hermetic package is designed to be mounted either in vertical or flat positions on a PC board, thus enabling the sensing directions of the accelerometer to be parallel or perpendicular to the plane of the PC board for front and side air bag applications. the package has been modeled for thermal stress induced during assembly and operating conditions. the dynamics of the package was determined using static, harmonic, modal, random vibration and transient dynamic modeling. Testing of the mounted package on the shaker shows flat frequency response to 4.5kHz. Temperature cycling on the unit between -40° and 85°C shows no failures or performance degradation over 2400 temperature cycles.
Combinational logic synthesis is a very important but computationally expensive phase of VLSI system design. parallelprocessing offers an attractive solution to reduce this design cycle rime. In this paper we describ...
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Combinational logic synthesis is a very important but computationally expensive phase of VLSI system design. parallelprocessing offers an attractive solution to reduce this design cycle rime. In this paper we describe ProperMIS, a portable parallel algorithm for logic synthesis based on the MIS multi-level logic synthesis system. As part of this work, we have developed novel parallelalgorithms for the different logic transformations of the MIS system. Our algorithm uses art asynchronous message-driven computing model with no synchronizing barriers separating phases of parallel computation. the algorithm is portable across a wide variety of parallelarchitectures, and is built around a well-defined sequential algorithm interface, so that we can benefit from future expansion of the sequential algorithm. We present results on several MCNC and ISCAS benchmark circuits for a variety of shared memory and distributed processingarchitectures. Our implementation produces speedups of an average of 4 on 8 processors.< >
the architectures of general purpose digital signal processors fail to deliver acceptable performance for multichannel signal processing. this paper describes a 40K transistor execution unit that is optimised for the ...
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the architectures of general purpose digital signal processors fail to deliver acceptable performance for multichannel signal processing. this paper describes a 40K transistor execution unit that is optimised for the processing of multichannel signals. the signal processor incorporates two 12 bit array multipliers and a 128 deep programmable delay line. To facilitate the programming of the device, it is designed to function as a memory mapped peripheral to a 16/32 bit microprocessor. It supports online diagnostics through the incorporation of shadow accumulators. It is fabricated in SCL's 2/spl mu/m double metal CMOS process and packaged in a 144 pin CPGA.
the paper presents the design of a VLSI fuzzy processor which is capable of performing fuzzy inferences based on the /spl alpha/-level sets theory. the use of the /spl alpha/-level sets family to represent fuzzy sets ...
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the paper presents the design of a VLSI fuzzy processor which is capable of performing fuzzy inferences based on the /spl alpha/-level sets theory. the use of the /spl alpha/-level sets family to represent fuzzy sets allows a considerable saving of memory resources if compared with conventional fuzzy inference methods which use membership functions to represent fuzzy sets. the main features of the architecture presented are parallelism and scalability. the processor comprises a set of units which work parallelly and asynchronously to process the various rules. the structure is easy to scale up, as an increase in the number of processing units does not produce bottlenecks in performance. the performance obtainable is about 300 KFLIPS, with a clock frequency of 50 MHz, 8 input variables, either crisp or fuzzy, and an 8 bit resolution.
In this paper we discuss a new automatic test scheduling system for architecturesthat use separate control and data-paths. MUlti-STage-Combinational Testing (MUSTC-Testing) at the Register-Transfer Level significantl...
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In this paper we discuss a new automatic test scheduling system for architecturesthat use separate control and data-paths. MUlti-STage-Combinational Testing (MUSTC-Testing) at the Register-Transfer Level significantly eases test generation and can be used in lieu of or to complement sequential test generation at the gate level. We provide a system with eleven signal types to perform test scheduling at the RT level which allows module level pre-computed test sets to be directly used for testing. A test scheduler is then described along withthe results obtained.
In this paper we present proposals of some basic synchronous fuzzy circuits which are of help in the design of fuzzy processors. Our proposal is a compromise between a digital and an analog solution. We discretize the...
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In this paper we present proposals of some basic synchronous fuzzy circuits which are of help in the design of fuzzy processors. Our proposal is a compromise between a digital and an analog solution. We discretize the degrees of membership and make each elementary operator regenerate the valid levels We thus obtain circuits which virtually make no mistakes, regardless of the number of cascading stages and retroactions. So these circuits exhibit high noise immunity. this means that these "fuzzy-gates" are robust. As the fuzzy-gates proposed use a CMOS technology similar to that of the digital approach, they share the performance of the latter as far as dissipated power is concerned.
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