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检索条件"任意字段=8th International Conference on Algorithms and Architectures for Parallel Processing"

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DESIGN OF A VLSI parallel PROCESSOR FOR FUZZY COMPUTING

DESIGN OF A VLSI PARALLEL PROCESSOR FOR FUZZY COMPUTING

引用

Proceedings of the 8th international conference on VLSI Design

作者： Ascia, G. Catania, V. Istituto di Informatica e Telecomunicazione Facoltà di Ingegneria Università di Catania V.le A.Doria 6 Catania95125 Italy

the paper presents the design of a VLSI fuzzy processor which is capable ofperforming fuzzy inferences based on the -level sets theory. the use of the a-level sets family to represent fuzzy sets allows a considerable saving of memory resources if compared with conventional fuzzy inference methods which use membership functions to represent fuzzy sets. the main features of the architecture presented are parallelism and scalability. the processor comprises a set of units which work parallelly and asynschronously to process the various rules. the structure is easy to scale up, as an increase in the number of processing units does not produce bottlenecks in performance. the performance obtainable is about 300 KFLIPS, with a clock frequency of 50 Mhz, 8 input variables, either crisp or fuzzy, and an 8-bit resolution. © 1995 IEEE.

关键词： Membership functions

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Evaluating digital angles by a parallel diffusion process 8th

引用

8th international conference on Image Analysis and processing, ICIAP 1995

作者： Cantoni, V. Cinque, L. Levialdi, S. Lombardi, L. Dipartimento di Informatica e Sistemistica Universita’ di Pavia Via Abbiategrasso 209 Pavia27100 Italy Dipartimento di Scienze dell’Informazione Universita’ "La Sapienza" di Roma Via Salaria 113 Roma00198 Italy

ISBN: (纸本)3540602984

this paper describes a new method that uses the diffusion-like process to classify angles in a image. the proposed method exploits the curvature value of a contour line to characterize the correspondent angle. the effectiveness of the new method is illustrated with the results of experiments for a number different angle types. © Springer-Verlag Berlin Heidelberg 1995.

关键词： Computers

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Performance engineering of distributed software process architectures 8th

引用

8th international conference on Modelling Techniques and Tools for Computer performance Evaluation, Performance Tools 1995 and 8th GI/ITG conference on Measuring, Modelling and Evaluating Computing and Communication Systems, MMB 1995

作者： Hills, Greg Rolia, Jerome Serazzi, Giuseppe School of Computer Science Carleton University OttawaONKlS 5B6 Canada Department of Systems and Computer Engineering Carleton University OttawaONKlS 5B6 Canada Dipartmento di Elettronica e Informazione Politecnico di Milano Italy

ISBN: (纸本)9783540603009

An important goal of a system's development team is to provide a software structure that evolves gracefully with its workload's intensity and characteristics, and the technologies that support the system. We describe a computationally efficient technique that helps us recognize potential software bottlenecks in a distributed software system over a range of workload conditions. Using this technique, software changes needed to support the workload over time can be identified early. Support for these software changes can be planned in advance and built into the system's architecture. the engineering structures from the Reference Model for Open Distributed processing (RM-ODP) are used as the basis for our software performance modelling. A case study is given that demonstrates how the proposed technique can be applied when implementing a distributed application in an environment such as the Open Software Foundation's (OSF) Distributed Computing Environment (DCE). © Springer-Verlag Berlin Heidelberg 1995.

关键词： Software architecture

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Object-oriented expert systems parallel knowledge processing in a CORBA-based architecture

Object-oriented expert systems parallel knowledge processing...

引用

IEEE international conference on algorithms and architectures for parallel processing (ICAP)

作者： th. Flor U. Eisenecker P. Siembor Dept. of Med. Inf. Tech. Univ. Ilmenau Germany Department of Evoltdionary Systems AG Research and Technology Ulm Germany Departmentrhnrm of Medical Infomtia Technical University슠of슠Ilmenau Ilmenau Germany

Knowledge based systems (KBS) of first generation are characterized by the separation of domain specific knowledge and general problem solving strategies. Such systems lack of the following important abilities: knowledge acquisition according different paradigms of representation and processing, definition of deep knowledge caused by physiological processes of reasoning, and management of different abstraction levels. Next generation KBS provide a bases from managing these problems. Essential characteristics of this new systems are modularization of knowledge, distribution of knowledge across different hardware and software resources, and use of object-oriented technology for integrating symbolic and subsymbolic knowledge on different levels of abstraction.< >

关键词： Expert systems Knowledge based systems Character generation Medical expert systems Problem-solving Knowledge management Access protocols Hardware Communication system software Communication system control

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Multilayer ceramic package for silicon micromachined accelerometers

Multilayer ceramic package for silicon micromachined acceler...

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Proceedings of the 1995 8th international conference on Solid-State Sensors and Actuators and Eurosensors IX. Part 1 (of 2)

作者： Koen, Edward Pourahmadi, Farzad Terry, Stephen EG&G IC Sensors Milpitas United States

A novel ceramic package for a two-chip silicon accelerometer and the signal conditioning ASIC chip assembly has been developed with the advantage of being directly mounted on a PC board thus eliminating the need for additional mounting structures for automotive airbag applications. the hermetic package is designed to be mounted either in vertical or flat positions on a PC board, thus enabling the sensing directions of the accelerometer to be parallel or perpendicular to the plane of the PC board for front and side air bag applications. the package has been modeled for thermal stress induced during assembly and operating conditions. the dynamics of the package was determined using static, harmonic, modal, random vibration and transient dynamic modeling. Testing of the mounted package on the shaker shows flat frequency response to 4.5kHz. Temperature cycling on the unit between -40° and 85°C shows no failures or performance degradation over 2400 temperature cycles.

关键词： Microelectronic processing

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parallel algorithms for logic synthesis using the MIS approach

Parallel algorithms for logic synthesis using the MIS approa...

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international Symposium on parallel processing

作者： K. De L.A. Chandy S. Roy S. Parkes P. Banerjee LSI Logic Corporation Milpitas CA USA University of Illinois Urbana IL USA Sierra Vista Research Inc. Santa Clara CA USA

Combinational logic synthesis is a very important but computationally expensive phase of VLSI system design. parallel processing offers an attractive solution to reduce this design cycle rime. In this paper we describe ProperMIS, a portable parallel algorithm for logic synthesis based on the MIS multi-level logic synthesis system. As part of this work, we have developed novel parallel algorithms for the different logic transformations of the MIS system. Our algorithm uses art asynchronous message-driven computing model with no synchronizing barriers separating phases of parallel computation. the algorithm is portable across a wide variety of parallel architectures, and is built around a well-defined sequential algorithm interface, so that we can benefit from future expansion of the sequential algorithm. We present results on several MCNC and ISCAS benchmark circuits for a variety of shared memory and distributed processing architectures. Our implementation produces speedups of an average of 4 on 8 processors.< >

关键词： parallel algorithms Concurrent computing Algorithm design and analysis Logic design parallel architectures Circuit synthesis Logic circuits Design optimization Very large scale integration Network synthesis

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A single chip, pipelined, cascadable, multichannel, signal processor

A single chip, pipelined, cascadable, multichannel, signal p...

引用

international conference on VLSI Design

作者： S. Krishnakumar P. Suresh S. Sadashiva Rao M.P. Pareek R. Gupta Semiconductor Complex Limited India Bangalore India University of Western Australia Perth Australia ARCUS Bangalore India

the architectures of general purpose digital signal processors fail to deliver acceptable performance for multichannel signal processing. this paper describes a 40K transistor execution unit that is optimised for the processing of multichannel signals. the signal processor incorporates two 12 bit array multipliers and a 128 deep programmable delay line. To facilitate the programming of the device, it is designed to function as a memory mapped peripheral to a 16/32 bit microprocessor. It supports online diagnostics through the incorporation of shadow accumulators. It is fabricated in SCL's 2/spl mu/m double metal CMOS process and packaged in a 144 pin CPGA.

关键词： Signal processing Finite impulse response filter Delay lines Filter bank Adders Digital signal processors Array signal processing Digital signal processing chips Transfer functions Pipeline processing

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Design of a VLSI parallel processor for fuzzy computing

Design of a VLSI parallel processor for fuzzy computing

引用

international conference on VLSI Design

作者： G. Ascia V. Catania Istituto di Informatica e Telecomunicazione Facolta di Ingegneria Università di Catania Catania Italy

the paper presents the design of a VLSI fuzzy processor which is capable of performing fuzzy inferences based on the /spl alpha/-level sets theory. the use of the /spl alpha/-level sets family to represent fuzzy sets allows a considerable saving of memory resources if compared with conventional fuzzy inference methods which use membership functions to represent fuzzy sets. the main features of the architecture presented are parallelism and scalability. the processor comprises a set of units which work parallelly and asynchronously to process the various rules. the structure is easy to scale up, as an increase in the number of processing units does not produce bottlenecks in performance. the performance obtainable is about 300 KFLIPS, with a clock frequency of 50 MHz, 8 input variables, either crisp or fuzzy, and an 8 bit resolution.

关键词： Very large scale integration Concurrent computing Fuzzy sets Fuzzy set theory Set theory parallel processing Scalability Clocks Frequency Input variables

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MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level

MUSTC-Testing: Multi-Stage-Combinational Test scheduling at ...

引用

international conference on VLSI Design

作者： S. Yadavalli I. Pomeranz S.M. Reddy Department of Electrical and Computer Engineering University of Iowa IA USA

In this paper we discuss a new automatic test scheduling system for architectures that use separate control and data-paths. MUlti-STage-Combinational Testing (MUSTC-Testing) at the Register-Transfer Level significantly eases test generation and can be used in lieu of or to complement sequential test generation at the gate level. We provide a system with eleven signal types to perform test scheduling at the RT level which allows module level pre-computed test sets to be directly used for testing. A test scheduler is then described along with the results obtained.

关键词： Circuit testing System testing Sequential analysis Circuit faults Processor scheduling Hardware design languages Registers Circuit synthesis Multiplexing Digital signal processing

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Analog gates for a VLSI fuzzy processor

Analog gates for a VLSI fuzzy processor

引用

international conference on VLSI Design

作者： V. Catania M. Russo Istituto di Informatica e Telecomunicazioni. Facoltà d'Ingegneria Università di Catania Italy

In this paper we present proposals of some basic synchronous fuzzy circuits which are of help in the design of fuzzy processors. Our proposal is a compromise between a digital and an analog solution. We discretize the degrees of membership and make each elementary operator regenerate the valid levels We thus obtain circuits which virtually make no mistakes, regardless of the number of cascading stages and retroactions. So these circuits exhibit high noise immunity. this means that these "fuzzy-gates" are robust. As the fuzzy-gates proposed use a CMOS technology similar to that of the digital approach, they share the performance of the latter as far as dissipated power is concerned.

关键词： Very large scale integration Pipelines Voltage Proposals CMOS technology Fuzzy sets parallel processing Analog-digital conversion CMOS digital integrated circuits CMOS logic circuits

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