检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

2,768 篇 会议
57 册 图书
47 篇 期刊文献

馆藏范围

2,870 篇 电子文献
2 种 纸本馆藏

日期分布

学科分类号

2,015 篇 工学
- 1,780 篇 计算机科学与技术...
- 943 篇 软件工程
- 297 篇 信息与通信工程
- 293 篇 电气工程
- 246 篇 电子科学与技术（可...
- 95 篇 控制科学与工程
- 52 篇 机械工程
- 49 篇 生物工程
- 44 篇 光学工程
- 41 篇 生物医学工程（可授...
- 37 篇 仪器科学与技术
- 28 篇 动力工程及工程热...
- 27 篇 化学工程与技术
- 21 篇 土木工程
- 20 篇 力学（可授工学、理...
- 19 篇 材料科学与工程（可...
- 18 篇 建筑学
541 篇 理学
- 385 篇 数学
- 106 篇 物理学
- 56 篇 生物学
- 48 篇 系统科学
- 32 篇 化学
- 32 篇 统计学（可授理学、...
197 篇 管理学
- 121 篇 管理科学与工程(可...
- 81 篇 图书情报与档案管...
- 56 篇 工商管理
51 篇 医学
- 42 篇 临床医学
- 16 篇 基础医学(可授医学...
19 篇 文学
17 篇 经济学
- 17 篇 应用经济学
15 篇 法学
- 14 篇 社会学
12 篇 农学
4 篇 教育学
3 篇 军事学

主题

342 篇 parallel process...
200 篇 parallel process...
193 篇 computer archite...
157 篇 graphics process...
153 篇 parallel archite...
112 篇 parallel algorit...
108 篇 graphics process...
106 篇 hardware
86 篇 image processing
78 篇 computational mo...
73 篇 signal processin...
71 篇 concurrent compu...
66 篇 instruction sets
65 篇 algorithm design...
65 篇 multicore proces...
63 篇 field programmab...
60 篇 parallel program...
59 篇 parallel computi...
53 篇 gpu
49 篇 digital signal p...

机构

10 篇 natl univ def te...
8 篇 college of compu...
6 篇 hosei univ dept ...
6 篇 college of compu...
5 篇 univ aizu dept c...
5 篇 national univers...
5 篇 natl univ def te...
5 篇 city university ...
5 篇 science and tech...
4 篇 chinese acad sci...
4 篇 school of comput...
4 篇 carleton univ sc...
4 篇 univ chinese aca...
4 篇 school of comput...
4 篇 charles univ pra...
4 篇 department of co...
4 篇 school of comput...
4 篇 hainan internati...
4 篇 purple mountain ...
4 篇 department of co...

作者

10 篇 liu jie
9 篇 jack dongarra
8 篇 roman wyrzykowsk...
7 篇 wang qinglin
7 篇 konrad karczewsk...
7 篇 quintana-orti en...
6 篇 gepner pawel
6 篇 peng shietung
6 篇 li kuan-ching
6 篇 li yamin
6 篇 chu wanming
6 篇 prasanna viktor ...
6 篇 rothermel kurt
6 篇 yang chao-tung
5 篇 dongarra jack
5 篇 olas tomasz
5 篇 hannig frank
5 篇 wanlei zhou
5 篇 qian depei
5 篇 ewa deelman

语言

2,845 篇 英文
16 篇 其他
13 篇 中文
1 篇 俄文

检索条件"任意字段=8th International Conference on Algorithms and Architectures for Parallel Processing"

共 2872 条记录，以下是2641-2650 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Approximate Sorting Check Node processing in Non-Binary LDPC Decoders

Approximate Sorting Check Node Processing in Non-Binary LDPC...

引用

IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Dimitris Chytas Vassilis Paliouras University of Patras Patras Greece

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

this paper proposes the use of parallel approximate sorting networks in Non-Binary LDPC decoders and quantifies their impact in terms of performance and complexity. Motivated by the messages truncation concept of the Extended Min Sum (EMS) algorithm and the reduction it induces on the decoding complexity, we seek for an approximate parallel sorting strategy for the Elementary Check Node (ECN) Unit processing in the EMS algorithm. We quantify the impact of parallel approximate sorting on both error correction decoding performance and hardware complexity. Bubble check sorting methods are compared to proposed parallel approximate sorting techniques in terms of BER vs. noise plots. Furthermore hardware synthesis results are provided to demonstrate the effects of parallel sorting networks on area and throughput. In certain cases of practical interest, a modest degradation of 0.2 dB in coding gain is imposed; however due to proposed parallel approximate sorters, the latency of ECN can be reduced by up to a factor of two or be logarithmic to the input sequence length, in certain architectures. To better illustrate the impact of the proposed techniques, a complete NB-LDPC decoder has been implemented and used for evaluation; it is found that a substantial reduction in the number of clock cycles required per decoding iteration is achieved by the proposed techniques, more than 50% in certain cases.

关键词： Sorting Decoding Complexity theory Parity check codes Approximation algorithms Degradation Signal to noise ratio

来源：评论

学校读者我要写书评

暂无评论

A C++ Library for Memory Layout and Performance Portability of Scientific Applications 28th

A C++ Library for Memory Layout and Performance Portabilit...

引用

28th international European conference on parallel and Distributed Computing , Euro-Par 2022

作者： Incardona, Pietro Gupta, Aryaman Yaskovets, Serhii Sbalzarini, Ivo F. Technische Universität Dresden Faculty of Computer Science Dresden Germany Max Planck Institute of Molecular Cell Biology and Genetics Dresden Germany Center for Systems Biology Dresden Dresden01307 Germany Center for Scalable Data Analytics and Artificial Intelligence ScaDS.AI Dresden/Leipzig Germany

ISBN: (纸本)9783031312083

We present a C++14 library for performance portability of scientific computing codes across CPU and GPU architectures. Our library combines generic data structures like vectors, multi-dimensional arrays, maps, graphs, and sparse grids with basic, reusable algorithms like convolutions, sorting, prefix sum, reductions, and scan. the memory layout of the data structures is adapted at compile-time using tuples with optional memory mirroring between CPU and GPU. We combine this transparent memory mapping with generic algorithms under two alternative programming interfaces: a CUDA-like kernel interface for multi-core CPUs, Nvidia GPUs, and AMD GPUs, as well as a lambda interface. We validate and benchmark the presented library using micro-benchmarks, showing that the abstractions introduce negligible performance overhead, and we compare performance against the current state of the art. © 2023, the Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

Efficient architectures for Planar and DC modes of Intra Prediction in HEVC

Efficient Architectures for Planar and DC modes of Intra Pre...

引用

international conference on Signal processing and Integrated Networks (SPIN)

作者： Lakshmi P. Aparna Department of Electronics and Communication National Institute of Technology Surathkal Karnataka India

ISBN: (数字)9781728154756

ISBN: (纸本)9781728154763

High efficiency video coding (HEVC) handles the ever increasing global video content with better compression efficiency. Complex partition and increased number of angular modes in intra prediction is one of the factors responsible to achieve this but at the expense of complex computations. In this work, we propose two hardware architectures, parallel Pipelined Architecture (PPA), and parallel Datapath Architecture (PDA) for the planar and direct current (DC) modes of intra prediction in HEVC. PPA supports a combination of pipelining and parallel schemes, reuses the multipliers to reduce the hardware resources. PDA includes datapath0 for planar mode and datapath1 for DC mode. they function in parallel. they support all the block sizes and implemented on Artix-7 field programmable gate array (FPGA). the implemented results show that PDA uses 20% fewer resources for block size 4, while PPA uses 20%, 46%, and 62% fewer resources for block sizes 8, 16, and 32, respectively. Detailed synthesis results show that PPA and PDA achieve a throughput of 8 pixels/clock cycle and hence can support 4K videos at 30 frames per second.

关键词： Computer architecture Streaming media Hardware Handheld computers Field programmable gate arrays throughput Encoding

来源：评论

学校读者我要写书评

暂无评论

A reconfigurable architecture specific for the butterfly computing

A reconfigurable architecture specific for the butterfly com...

引用

international conference on ASIC

作者： Jing Xie Kai Fan Zhigang Mao Qin Wang Chao Yang Wen Zhu Suliang Wang School of Microelectronics Shanghai Jiaotong University Shanghai China

Morphosys is a reconfigurable single instruction multiple data (SIMD) architecture mainly composing of host core processor, reconfigurable cells array, frame buffer, context memory and direct memory access (DMA) module. As a common SIMD-based coarse-grained reconfigurable architecture, each context configuration and operation is based on the whole row or column function, which may be inefficient in some applications such as butterfly computing. In this paper, an improved reconfigurable architecture is proposed specific for butterfly computing application. the main work includes interconnection network design optimization, context memory architecture redefinition with quadrant binding, DMA channel addition and some other corresponding modification in reconfigurable cell. With these improvements, the new architecture can implement typical butterfly computing with cycle count about 5.53%~18.9% less than Morphosys.

关键词： Reconfigurable architectures Computer architecture Embedded computing Embedded system Digital signal processing Concurrent computing Computer applications Design optimization High performance computing Computer aided instruction

来源：评论

学校读者我要写书评

暂无评论

parallel Vertex Color Update on Large Dynamic Networks

Parallel Vertex Color Update on Large Dynamic Networks

引用

international conference on High Performance Computing

作者： Arindam Khanda Sanjukta Bhowmick Xin Liang Sajal K. Das Missouri University of Science and Technology Rolla USA University of North Texas Denton USA

We present the first GPU-based parallel algorithm to efficiently update vertex coloring on large dynamic networks. For single GPU, we introduce the concept of loosely maintained vertex color update that reduces computation and memory requirements. For multiple GPUs, in distributed environments, we propose priority-based ordering of vertices to reduce the communication time. We prove the correctness of our algorithms and experimentally demonstrate that for graphs of over 16 million vertices and over 134 million edges on a single GPU, our dynamic algorithm is as much as 20x faster than state-of-the-art algorithm on static graphs. For larger graphs with over 130 million vertices and over 260 million edges, our distributed implementation with 8 GPUs produces updated color assignments within 160 milliseconds. In all cases, the proposed parallel algorithms produce comparable or fewer colors than state-of-the-art algorithms.

关键词： Image color analysis Heuristic algorithms High performance computing Memory management Graphics processing units parallel algorithms Kernel

来源：评论

学校读者我要写书评

暂无评论

Pipeline Architecture for N==K*2L Bit Modular ALU: Case Study between Current Generation Computing and Vedic Computing

Pipeline Architecture for N==K*2L Bit Modular ALU: Case Stud...

引用

international conference for Convergence of Technology (I2CT)

作者： G.N. Chiranjeevi Subhash Kulkarni Department of Electronics and Communication Engineering PESIT-Bangalore South Campus Bangalore Affiliated to Visvesvaraya Technological University Belagavi Karnataka India

ISBN: (纸本)9781728188768;9781728188775

this paper describes a design architecture that performs mathematical operations using Vedic sutra for upward compatibility in pipeline manner. In spite of increasing the area, performance and reducing power, Vedic architecture have observed to be inherently compatible with higher efficiency for pipeline architecture. However Vedic architecture leads to additional flexibility starting from 2-bit base modules to 8-bit modules (L=1,2,3) and pipeline can be compactable to any base modules for any given length. Many researchers proposed arithmetic algorithms at simulation level using vedic sutra. these algorithm have been evaluated with better performance, area and speed. the literature has been widely found to be towards individual arithmetical operators like multiplier, square and cube and so on. A consolidated computing architecture, especially N-bit ALU is yet be realized Generalized N-bit ALU, can always be realized using pipeline modular architecture. the proposition is on realizing N-bit using `2^L, as base modules using `K' modules in pipelining. the authors have extensively verified modular architecture for 4-Bit modules for 16 bit and 32 bit pipelined operations. Individually multiplication using Urdhva Tiryakbhyam, division using Dhwajanka sutra, square using Dwandwayoga sutra. MAC unit which involves multiplication algorithms used in FFT and IFFT using sutras of Vedic mathematics and it is possible to achieve reduce version interms of speed and delay, compared to different generations of ALU the authors are now exploring N-bit ALU architecture FPGA implementation using Vedic sutras with flexible modular pipeline architecture and mainly targeted for Digital Signal processing applications.

关键词： Computational modeling Signal processing algorithms Process control Computer architecture Digital signal processing parallel architectures Delays

来源：评论

学校读者我要写书评

暂无评论

DReNoC: A dynamically reconfigurable computing system based on network-on-chip

DReNoC: A dynamically reconfigurable computing system based ...

引用

international conference on ASIC

作者： Ying-Chun Chen Gao-Ming Du Luo-Feng Geng Duo-Li Zhang Ming-Lun Gao Institute of VLSI Design Hefei University of Technology Hefei China

A dynamically reconfigurable computing system based on network-on-chip (DReNoC) is proposed, which consists of computing nodes and communication nodes. the computing node is a complete coarse-grained dynamically reconfigurable SoC named DReSoC. And the DReSoCs communicate with each other through on chip network routers. the proposed DReNoC has been implemented on the ALTERA STRATIX II EP2S180 DSP development board with 48063 Combinational ALUTs and 26211 logic registers. Experimental result of 8?8 matrix sequential matrix multiplications showed that, compared with a single-core system-on-chip (SoC) based on the standard Nios II processor, the speed-up ratio can reach 124.91.

关键词： Computer networks Network-on-a-chip Streaming media Computer architecture Energy consumption Concurrent computing parallel processing Circuit synthesis Sun High performance computing

来源：评论

学校读者我要写书评

暂无评论

parallel Approach to Fuzzy Vector Quantization for Image Compression

Parallel Approach to Fuzzy Vector Quantization for Image Com...

引用

ACIS international conference on Software Engineering, Artificial Intelligence, Networking, and parallel/Distributed Computing (SNPD)

作者： Huynh Van Luong Yong-Min Kim Byung-Kook Kim Jong-Myon Kim Cheol-Hong Kim School of Computer Engineering and Information Technology University of Ulsan Ulsan Korea School of Electronics and Computer Engineering Chonnam National University Gwangju Korea

Fuzzy clustering based vector quantization algorithm has been widely used in the field of data compression since the use of fuzzy clustering analysis in the early stages of a vector quantization process can make this process less sensitive to initialization. However, the process of fuzzy clustering is computationally very intensive because of its complex framework for the quantitative formulation of the uncertainty involved in the training vector space. To overcome the computational burden of the process, we introduce a parallel implementation of Fuzzy Vector Quantization (FVQ) using a representative data parallel architecture which consists of 4,096 processing elements (PEs). Our parallel approach provides a computationally efficient solution with the 4,096 PEs by employing an effective vector assignment strategy for the transition from soft to crisp decisions during the clustering process. Experimental results show that our parallel approach provides 1000times greater performance and 100times higher energy efficiency than other implementations using commercial processors such as ARM families.

关键词： Vector quantization Image coding parallel architectures Concurrent computing Energy efficiency Distributed computing Clustering algorithms Algorithm design and analysis Data compression Uncertainty

来源：评论

学校读者我要写书评

暂无评论

Performance optimization of Histogram Equalization for digital images using modern imaging

Performance optimization of Histogram Equalization for digit...

引用

international conference on Computing and Networking Technology (ICCNT)

作者： G Kalyan Kumar Anita Titus R.S. Vijayashanthi M Shalini M Dinesh Department of CSE Rajalakshmi Institute of Technology Chennai Department of ECE Jeppiaar University Chennai Department of ECE S.A. Engineering College Chennai Department of CSE St. Joseph’s College of Engineering Chennai Department of VLSI Microelectronics Saveetha School of Engineering Saveetha Institute of Medical and Technical Sciences (SIMATS) Saveetha University Chennai

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

Histogram equalization is a method of contrast adjustment in image processing using the image’s histogram. However, as modern imaging systems become more complex, these traditional algorithms for histogram equalization are no longer efficient. In response to this problem, researchers have studied several strategies for improving the performance of histogram equalization in digital images. An option is to use parallel processing and multi-threading approaches to distribute the computational burden, thereby speeding up the execution of histogram equalization. Another methodology includes using machine learning algorithms to adapt histogram equalization parameters according to the input image. Furthermore, using advanced hardware architectures like Field Programmable Gate Arrays (FPGA), Graphic processing Units (GPU), or Application Specific Integrated Circuits can significantly enhance the speed and efficiency of a Histogram Equalization. the performance optimization techniques have provided encouraging results, which significantly refine image processing time and visual perception. Modern imaging systems may benefit tremendously from their use in the new age.

关键词： Histograms Machine learning algorithms Digital images Surveillance Graphics processing units parallel processing Real-time systems Optimization Field programmable gate arrays Visual perception

来源：评论

学校读者我要写书评

暂无评论

High-Performance Matrix Multiplication on the New Generation Shenwei Processor

High-Performance Matrix Multiplication on the New Generation...

引用

IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Le Xu Hong An Junshi Chen Pengfei Zhang School of Computer Science and Technology University of Science and Technology of China Hefei China

As a critical operation in numerical computing, matrix multiplication is widely used in many high-performance applications. the new generation Shenwei processor is the newest many-core processor with powerful computing capacity, thus it's necessary to enable highly efficient matrix multiplication on it. In this paper, we present a detailed implementation of double-precision matrix multiplication on Shenwei processor and further perform deep optimizations in terms of both memory access and computing. We employ a three-level task partitioning scheme mapping blocked matrix multiplication to each mem-ory hierarchy to improve computational parallelism and data reusability. And the dual broadcasting algorithm enables efficient parallel computing on chip. For further optimization, we present a three-level latency hiding strategy to bridge the performance gap between computing and memory access, where the hybrid data prefetch effectively hides DMA memory access and RMA communication costs. And the adaptive blocking algorithm is proposed for sake of the generality of algorithms towards various matrix sizes and shapes. High-performance matrix multiplication is highly correlated with the compute kernel, and we propose the register-buffering instruction scheduling with latency hiding strategy to maximize pipeline efficiency. the experiments show that the performance of our algorithm can reach 2 TFLOPS at large scales, near the theoretical peak performance. And the hybrid prefetch can improve performance by 82 %, while the adaptive blocking not only improves performance but also smoothes the performance jitter of irregular matrix multi-plications. the compute kernel with instruction scheduling is highly optimized and can achieve more than 380% performance improvement.

关键词： Bridges Costs Processor scheduling Prefetching parallel processing Jitter Broadcasting

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共288页 << < 261 262 263 264 265 266 267 268 269 270 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：