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Optimized Computation for Determinant of Multivariate Polynomial Matrices on GPGPU

Optimized Computation for Determinant of Multivariate Polyno...

引用

IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Liangyu Chen Jianjun Wei Zhenbing Zeng Min Zhang Shanghai Key Lab of Trustworthy Computing East China Normal University Shanghai China Department of Computer Science and Engineering Washington University in St. Louis St Louis USA Department of Mathematics Shanghai University Shanghai China

the determinant of the matrix is a fundamental concept in linear algebra and has various applications in research and engineering. Compared to the easy-calculating numeric matrix, a symbolic matrix with multivariate polynomial entries is hard to calculate because of immediate expression expansion, which often leads to drastic exhaustion of the physical memory. In this paper, we present a novel four-stage-approach to calculate the accurate determinant of multivariate polynomial matrices on GPGPU, through using the modular method, the Stockham Fast Fourier Transformation(FFT), the inverse FFT, and the Chinese Remainder theorem. In our approach, the computation tasks in each stage are deployed on GPGPU so that the calculation could be recovered without loss at any point in case of inevitable interruptions happened during the parallel processing. In addition, to control the parallel computation time, we propose a time prediction model for the computation of polynomial determinant according to the basic matrix attributes. the experiment results show that our approach owns substantial speedups compared to Maple, allowing memory and time usage in steady increments.

关键词： Computational modeling Memory management Linear algebra Predictive models parallel processing Task analysis

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De(con) Struction of the Lazy-F Loop: Improving Performance of Smith Waterman Alignment

De(con) Struction of the Lazy-F Loop: Improving Performance ...

引用

IEEE Symposium on Bioinformatics and Bioengineering (BIBE)

作者： Roman Snytsar Research and AI Microsoft Redmond USA

ISBN: (纸本)9781728146188

Striped variation of the Smith-Waterman algorithm is known as extremely efficient and easily adaptable for the SIMD architectures. However, the potential for improvement has not been exhausted yet. the popular Lazy-F loop heuristic requires additional memory access operations, and the worst-case performance of the loop could be as bad as the nonvectorized version. We demonstrate the progression of the lazy-F loop transformations that improve the loop performance, and ultimately eliminate the loop completely. Our algorithm achieves the best asymptotic performance of all scan-based SW algorithms O(n/p+log(p)), and is very efficient in practice.

关键词： Bioinformatics parallel processing Optimization Arrays Computational complexity Instruction sets

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Optimizing collective communications on SMP clusters

Optimizing collective communications on SMP clusters

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international conference on parallel processing (ICPP)

作者： Meng-Shiou Wu R.A. Kendall K. Wright Department of Electrical and Computer Engineering Scalable Computing Laboratory U.S. DOE Iowa State University Ames IA USA Scalable Computing Laboratory Ames Laboratory U.S. DOE Iowa State University Ames IA USA Department of Computer Science Scalable Computing Laboratory Ames Laboratory U.S. DOE Iowa State University Ames IA USA

We describe a generic programming model to design collective communications on SMP clusters. the programming model utilizes shared memory for collective communications and overlapping inter-node/intra-node communications, both of which are normally platform specific approaches. Several collective communications are designed based on this model and tested on three SMP clusters of different configurations. the results show that the developed collective communications can, with proper tuning, provide significant performance improvements over existing generic implementations. For example, when broadcasting an 8 MB message our implementations outperform the vendor's MPl/spl ***/Bcast by 35% on an IBM SP system, 51% on a G4 cluster, and 63% on an Intel cluster, the latter two using MPICH's MPl/spl ***/Bcast. With all-gather operations using 8 MB messages, our implementation outperform the vendor's MPI/spl ***/Allgather by 75% on the IBM SP, 60% on the Intel cluster, and 48% on the G4 cluster.

关键词： Laboratories US Department of Energy Clustering algorithms Design optimization Computer science Communication networks Testing Broadcasting Pipelines parallel architectures

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Design and Verification of High-Speed Radix-2 Butterfly FFT Module for DSP Applications

Design and Verification of High-Speed Radix-2 Butterfly FFT ...

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international conference on Trends in Electronics and Informatics (ICEI)

作者： Utsav Kumar Malviya Government Engineering College Bilaspur India

ISBN: (数字)9781728155180

ISBN: (纸本)9781728155197

Digital signal processing (DSP) processor is a key element of 4th Generation (4G) communication and Fast Fourier Transform (FFT) is an important operation of the modern Digital signal Processor (DSP). this work design an area and speed optimized FFT module for the DSP processor. Real-time computation of signals must meet real-time scenarios and highly requires to make computation faster as possible, hence a fast FFT proposed. Two types of methods can be used for FFT operation: first is Decimation in time (DIT) and second is Decimation in frequency (DIF). the operational speed of these algorithms depends on the multipliers used for computation. Multipliers in the FFT process are the key factor for the speed performance and if multiplier modifies in terms of area and speed overall FFT processor also performance gets an increase. this work design FFT processor with Vedic multiplier and new semi-pipelined Fast Fourier transform (SPFFT) with modified multiplication arrangement gave a provide area optimized hardware architecture. In conventional method, radix-2 2 had been used only for single-path delay feedback architectures. Later with many types of research works radix, 22 was extended to multipath delay commutation (MDC) architectures. this work design is provided for parallel operation of value 16 signal samples, Xilinx Vivado EDA is used for the implementation of this work. for emulation Zynq-7 FPGA board used.

关键词： Adders Random access memory Pipeline processing conferences Market research Informatics Digital signal processing

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On the parallel iterative finite difference algorithm for 2-D Poisson's equation with MPI cluster

On the parallel iterative finite difference algorithm for 2-...

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the international conference on Informatics and Systems (INFOS)

作者： N. H. Sweilam H. M. Moharram Sameh Ahmed Mathematics Department Faculty of Science Cairo University Giza Egypt

In this paper, a parallel iterative finite difference method (PIFD) for solving 2D Poisson's equation on a distributed system using Message Passing Interface (MPI) is investigated. this method is based on the domain decomposition method, where the 2D domain is divided into multiple sub-domains using horizontal and/or vertical axis depending on the available number of computer nodes. For interior points Poisson's equation is solved implicitly by four iterative schemes in combining with the boundary conditions. At the interface points of interior subdomains, Poisson's equation is solved by explicit iterative schemes. the proposed approach fulfills the suitability for the implementation on Linux PC cluster through the minimization of inter-process communication by restricting the exchange of data to the interface between the sub-domains. To examine the efficiency and accuracy of the iterative algorithm, several numerical experiments using different number of nodes of the Linux PC cluster are tested. the performance metrics clearly show the benefit of using the proposed approach on the Linux PC cluster in terms of execution time reduction and speedup with respect to the sequential running in a single PC.

关键词： Computers Program processors Poisson equations Iterative methods Finite difference methods Educational institutions parallel processing

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Method of 3D mesh reconstruction from point cloud using elementary vector and geometry analysis

Method of 3D mesh reconstruction from point cloud using elem...

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international conference on Digital Content, Multimedia Technology and its Applications (IDC)

作者： N. Wongwaen S. Tiendee C. Sinthanayothin Image Technology Laboratory National Electronics and Computer Technology Center Pathum Thani Thailand Department of Computing Faculty of Liberal Arts and Sciences Kasetsart University Nakhon Pathom Thailand

the method of three dimensional mesh reconstruction is used to supplementing the 3D reconstruction or 3D scanning method, which only provide with point cloud in 3D model. However, the 3D models in mesh mode illustrate clearer appearance and can be used to obtain more information. In addition, the 3D reconstruction has been previously developed by employing the digital fringe pattern projection where the output was formed in the point cloud. therefore, this paper presents the computerized algorithms to construct the 3D mesh from the point cloud. the algorithm can be done by firstly dividing the point cloud into small volume for parallel calculation. Next, the points in each small volume are connected, which becomes the submesh and then integrated them together. the submesh in each small volume is produced by creating the initial triangle and then expanding triangular construction continually from each side (base) which has been previously generated. the expanded triangles must be satisfied some certain constrains. the point cloud which is filtered from the STL file format was tested using proposed method. the mesh reconstruction is shown with reasonable result.

关键词： Computational modeling Graphics processing unit

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Using HPX and OP2 for Improving parallel Scaling Performance of Unstructured Grid Applications

Using HPX and OP2 for Improving Parallel Scaling Performance...

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international conference on parallel processing Workshops (ICPPW)

作者： Zahra Khatami Hartmut Kaiser J. Ramanujam The STE∥AR Group Baton Rouge Louisiana USA Center for Computation and Technology Louisiana State University

ISBN: (纸本)9781509028269

Computer scientists and programmers face the difficultly of improving the scalability of their applications while using conventional programming techniques only. As a base-line hypothesis of this paper we assume that an advanced runtime system can be used to take full advantage of the available parallel resources of a machine in order to achieve the highest parallelism possible. In this paper we present the capabilities of HPX - a distributed runtime system for parallel applications of any scale - to achieve the best possible scalability through asynchronous task execution [1]. OP2 is an active library which provides a framework for the parallel execution for unstructured grid applications on different multi-core/many-core hardware architectures [2]. OP2 generates code which uses OpenMP for loop parallelization within an application code for both single-threaded and multi-threaded machines. In this work we modify the OP2 code generator to target HPX instead of OpenMP, i.e. port the parallel simulation backend of OP2 to utilize HPX. We compare the performance results of the different parallelization methods using HPX and OpenMP for loop parallelization within the Airfoil application. the results of strong scaling and weak scaling tests for the Airfoil application on one node with up to 32 threads are presented. Using HPX for parallelization of OP2 gives an improvement in performance by 5%-21%. By modifying the OP2 code generator to use HPX's parallel algorithms, we observe scaling improvements by about 5% as compared to OpenMP. To fully exploit the potential of HPX, we adapted the OP2 API to expose a future and dataflow based programming model and applied this technique for parallelizing the same Airfoil application. We show that the dataflow oriented programming model, which automatically creates an execution tree representing the algorithmic data dependencies of our application, improves the overall scaling results by about 21% compared to OpenMP. Our results show

关键词： Automotive components parallel processing Scalability Programming Instruction sets Runtime Hardware

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Oneiric processing utilising the anticipatory classifier system

引用

8th international conference on parallel Problem Solving from Nature, PPSN 2004

作者： Holley, Julian C. Pipe, Anthony G. Carse, Brian Clares MHE Ltd Wells Somerset United Kingdom University of the West of England Bristol United Kingdom

ISBN: (纸本)3540230920

the cognitive abilities of the anticipatory classifier system (ACS) have already been successfully shown in earlier work [20]. this report takes inspiration from some philosophical ideas for the purpose of dreaming in animals and humans. this is supported by recent neurological studies that show that rats revisit recent situations in a way that suggests dreaming [25]. An extension is made to the ACS that uses the incomplete information contained in the classifier list as a basis for an abstract world model in which to interact or dream. the abstract thread or dream direction is an emergent property of the selection process, this can be used to recycle around well known states and reduce real world interaction. the system is applied to the classic T-maze experiment and demonstrates that considerably less interactions with the real world are required in order to develop a confident world model. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Philosophical aspects

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An efficient multicore implementation of planted motif problem

An efficient multicore implementation of planted motif probl...

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international conference on High Performance Computing & Simulation (HPCS)

作者： Naga Shailaja Dasari Ranjan Desh M. Zubair Department of Computer Science Old Dominion University Norfolk Virginia Old Dominion University Norfolk VA US

In this paper we propose a parallel algorithm for the planted motif problem that arises in computational biology. A variety of algorithms have been proposed in the literature to solve this problem. the drawback of all these algorithms is that they have been designed to work on serial computers; and are not suitable for parallelization on current multicore architectures. We have implemented the proposed algorithm on a 4 Quad-Core Intel Xeon X5550 2.67GHz processor for a total of 16 cores. We compare our performance results with the best performance results reported in the literature; and showed that the performance of our algorithm scales linearly with the number of cores. We also solved the (21, 8) challenging instance on 16 cores in 6.9 hrs.

关键词： Arrays Magnetic cores Indexes Memory management Multicore processing Iterative methods Algorithm design and analysis

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Hybrid Compiler and Hardware Approach to Mitigate Side-Channel Vulnerabilities in parallel GPU architectures

Hybrid Compiler and Hardware Approach to Mitigate Side-Chann...

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international conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC)

作者： Nelson Lungu Bibhuti Bhusan Dash Utpal De Chandra Bibek Bikram Dash Binod Kumar Pattanayak Sudhansu Shekhar Patra Electrical and Electronical Engineering University of Zambia Lusaka Zambia School of Computer Applications KIIT Deemed to be University Bhubaneswar India HealthWorksAI Bangalore India Department of Computer Science & Engineering ITER Siksha ‘O’ Anusandhan University Bhubaneswar Odisha India

ISBN: (数字)9798350376425

ISBN: (纸本)9798350376432

Graphics processing units (GPUs) have become ubiquitous in computing systems, from personal devices to data centres. their massively parallel architecture delivers tremendous performance for graphics and general-purpose workloads. However, the open nature of GPUs also introduces security vulnerabilities that can be exploited through side-channel attacks. Defending against such threats often incurs performance overhead, creating tradeoffs between security and speed. this article examines recent research analysing and mitigating GPU side channel attacks while maintaining acceptable performance and presented a multi-faceted defence strategy combining compiler transformations, runtime monitoring, and microarchitectural techniques to balance security and performance. the methodology integrates formal threat models, empirical side-channel evaluations, and rigorous benchmarking. It implements and evaluates prototypes demonstrating security improvement with minimal impact on representative workloads. the results provide promising directions for practical GPU security defences.

关键词： Performance evaluation threat modeling Runtime Microarchitecture Prevention and mitigation Graphics processing units Prototypes Side-channel attacks Security Protection

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