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A C++ Library for Memory Layout and Performance Portability of Scientific Applications 28th

A C++ Library for Memory Layout and Performance Portabilit...

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28th international European conference on parallel and Distributed Computing , Euro-Par 2022

作者： Incardona, Pietro Gupta, Aryaman Yaskovets, Serhii Sbalzarini, Ivo F. Technische Universität Dresden Faculty of Computer Science Dresden Germany Max Planck Institute of Molecular Cell Biology and Genetics Dresden Germany Center for Systems Biology Dresden Dresden01307 Germany Center for Scalable Data Analytics and Artificial Intelligence ScaDS.AI Dresden/Leipzig Germany

ISBN: (纸本)9783031312083

We present a C++14 library for performance portability of scientific computing codes across CPU and GPU architectures. Our library combines generic data structures like vectors, multi-dimensional arrays, maps, graphs, and sparse grids with basic, reusable algorithms like convolutions, sorting, prefix sum, reductions, and scan. the memory layout of the data structures is adapted at compile-time using tuples with optional memory mirroring between CPU and GPU. We combine this transparent memory mapping with generic algorithms under two alternative programming interfaces: a CUDA-like kernel interface for multi-core CPUs, Nvidia GPUs, and AMD GPUs, as well as a lambda interface. We validate and benchmark the presented library using micro-benchmarks, showing that the abstractions introduce negligible performance overhead, and we compare performance against the current state of the art. © 2023, the Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Graphics processing unit

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A sampled-analog rank-order-filter architecture

A sampled-analog rank-order-filter architecture

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： U. Cilingiroglu L.E. Dake Electrical Engineering Department Texas A and M University College Station TX USA Texas Instruments Inc. Dallas TX USA

We propose a sampled-analog rank-order filter (ROF) architecture of complexity O(n/sup 2/). It yields a very compact structure because the devices used are essentially of minimum geometry. Its sole active building block being the simple CMOS inverter, the circuit exhibits an excellent low-voltage compatibility. Furthermore, it can support a rail-to-rail input range. It is inherently fast due to the fully parallel signal processing, and the speed is expected to increase with technological scaling at the same rate as purely digital circuitry. Finally, it supports full programmability of the rank by means of an analog reference voltage. the ROF is based on a pair of multiple-winners-take-all (mWTA) circuits and a set of AND gates. the paper includes a description of the architecture and a detailed analysis of the mWTA. Most relevant design issues are addressed, and experimental results obtained from a fabricated ROF are presented.

关键词： Inverters Circuits Nonlinear filters Voltage Clocks Signal processing Capacitors Virtual reality Biomedical signal processing Application software

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Accelerating the Performance of Stochastic Encoding-based Computations by Sharing Bits in Consecutive Bit Streams

Accelerating the Performance of Stochastic Encoding-based Co...

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IEEE international conference on Application-specific Systems, architectures and Processors

作者： Peng Li David J. Lilja Department of Electrical and Computer Engineering University of Minnesota Twin Cities Minneapolis MN USA 55812

ISBN: (纸本)9781479904945

Stochastic encoding represents a value using the probability of ones in a random bit stream. Computation based on this encoding has good fault-tolerance and low hardware cost. However, one of its major issues is long processing time. We have to use a long enough bit stream to represent a value to guarantee that random fluctuations introduce only small errors to final computation results. For example, for most digital image processing algorithms, we need a 512-bit stream to represent an 8-bit pixel value stochastically to guarantee that the final computation error is less than 5%. To solve this issue, this paper proposes to share bits between adjacent bit streams to represent adjacent deterministic values. For example, in image processing applications, the bit stream which represents the current pixel value can share parts of the bits in the bit stream which represents the previous pixel value. We use an image contrast stretching algorithm to evaluate this method. Our experimental results show that the proposed methods can improve the performance by 90%.

关键词： Computer reliability fault tolerance logic design stochastic computing digital image processing bit stream Image processing Logic design Fault tolerance Drill bits IMAGE CONTRAST arithmetic errors image processing algorithm streams random fluctuations processing time Binary digits

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Improving parallel performance of ensemble learners for streaming data through data locality with mini-batching

Improving parallel performance of ensemble learners for stre...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Guilherme Cassales Heitor Gomes Albert Bifet Bernhard Pfahringer Hermes Senger Federal University of São Carlos Brazil University of Waikato New Zealand

ISBN: (纸本)9781728176505

Machine Learning techniques have been employed in virtually all domains in the past few years. New applications demand the ability to cope with dynamic environments like data streams with transient behavior. Such environments present new requirements like incrementally process incoming data instances in a single pass, under both memory and time constraints. Furthermore, prediction models often need to adapt to concept drifts observed in non-stationary data streams. Ensemble learning comprises a class of stream mining algorithms that achieved remarkable prediction performance in this scenario. Implemented as a set of (several) individual component classifiers whose predictions are combined to predict new incoming instances, ensembles are naturally amendable for task parallelism. Despite its relevance, an efficient implementation of ensemble algorithms is still challenging. For example, dynamic data structures used to model non-stationary data behavior and detect concept drifts cause inefficient memory usage patterns and poor cache memory performance in multi-core environments. In this paper, we propose a minibatching strategy which can significantly reduce cache misses and improve the performance of several ensemble algorithms for stream mining in multi-core environments. We assess our strategy on four different state-of-art ensemble algorithms applying four widely used machine learning benchmark datasets with varied characteristics. Results from two different hardware show speedups of up to 5X on 8-core processors with ensembles of 100 and 150 learners. the benefits come at the cost of changes in predictive performances.

关键词： Adaptation models Machine learning algorithms Multicore processing Heuristic algorithms Memory management parallel processing Prediction algorithms

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An Improvement of OpenMP Pipeline parallelism with the BatchQueue Algorithm

An Improvement of OpenMP Pipeline Parallelism with the Batch...

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international conference on parallel and Distributed Systems (ICPADS)

作者： thomas Preud'Homme Julien Sopena Gaël thomas Bertil Folliot LIP6 Paris France

In the context of multicore programming, pipeline parallelism is a solution to easily transform a sequential program into a parallel one without requiring a whole rewriting of the code. the OpenMP stream-computing extension presented by Pop and Cohen proposes an extension of OpenMP to handle pipeline parallelism. However, their communication algorithm relies on Multiple-producer-Multiple-Consumer queues, while pipelined applications mostly deal with linear chains of communication, i.e., with only a single producer and a single consumer. To improve the performance of the OpenMP stream-extension, we propose to add a more specialized Single-Producer-Single-Consumer communication algorithm called Batch Queue and to select it for one-to-one communication. Our evaluation shows that Batch Queue is then able to improve the throughput up to a factor 2 on an 8-core machine both for example application and real applications. Our study shows therefore that using specialized and efficient communication algorithms can have a significant impact on the overall performance of pipelined applications.

关键词： parallel processing Pipelines throughput Benchmark testing Synchronization Multicore processing Scalability

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Scalable processing in 5G Cloud-RAN Networks Using MapReduce Framework

Scalable Processing in 5G Cloud-RAN Networks Using MapReduce...

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New Technologies, Mobility and Security (NTMS)

作者： Ali M. Mahmood Adil Al-Yasiri School of Computing Science and Engineering University of Salford Greater Manchester UK

ISBN: (纸本)9781509029150

Cloud Radio Access Network (C-RAN) was introduced as a revolutionary architecture to meet the exponential expansion in data traffic for the current and future mobile networks. However, the centralized configuration of C-RAN brings many challenges. One of the key questions to address is how the channel state information (CSI) is acquired accurately in C-RAN for numerous access points and users. For the purpose of reducing the time of acquiring CSI in C-RAN, the MapReduce framework is proposed in this paper as a novel approach to minimize the overhead of acquiring CSI in the full centralized C-RAN architecture. the main contribution of this paper is employing parallel processing to improve the scalability of mobile networks using C-RAN. the results, which have been obtained through simulation, illustrate that it can maintain the scalability as well as save a significant amount of acquisition time without affecting the performance of network.

关键词： Antennas Computer architecture Mobile computing Cloud computing Estimation 5G mobile communication

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A Novel parallel processing Architecture for Deblocking Filter in H.264 Using Vertical MB Filtering Order

A Novel Parallel Processing Architecture for Deblocking Filt...

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2006 8th international conference on Solid-State and Integrated Circuit Technology

作者： Yue-Xi Zhao An-Ping Jiang SOC Lab Department of microelectronicsPeking University

An efficient paraUel processing method for deblocking filter design in H.264 video coding standard is presented in this paper. In order to reduce the memory reference and make the intermediate data reused as soon as possible,an advanced filtering order is taken,and read/write operation on external memory is executed in parallel with filtering computation. Furthermore,preloading operation is taken to reduce complexity of memory structure,and vertical MB processing order is used for improving the efficiency of intermediate data *** a result,the processing cycles of the proposed architecture with single-port memory architecture is reduced by 80.5%compared with the advanced architecture of previous proposals.

关键词： AVC Filter A Novel parallel processing Architecture for Deblocking Filter in H.264 Using Vertical MB Filtering Order

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AN SMPUMHEXAGONS-BASED MOTION ESTIMATION ALGORIthM FOR HETEROGENEOUS architectures

AN SMPUMHEXAGONS-BASED MOTION ESTIMATION ALGORITHM FOR HETER...

引用

IEEE international conference on Image processing

作者： Alvaro Garcia Rafael Rodriguez-Sanchez Jose Luis Martinez Albacete Research Institute of Informatics University of Castilla-La Mancha Depto. de Ingenieria y Ciencia de Computadores Universidad Jaume I (UJI)

ISBN: (纸本)9781479957521

Simplified Unsymmetrical Multi-Hexagon Search is one of the faster motion estimation algorithms for video coding available in the literature. It achieves a very good tradeoff between computational complexity and coding efficiency. In fact, the H.264/AVC reference software includes it, and it could easily be extended to the new video coding standard: High Efficiency Video Coding. this paper proposes a parallel algorithm which implements the Simplified Unsymmetrical Multi-Hexagon motion search in a graphic processing unit which serves as co-processor for the central processing unit. the results show a negligible rate distortion drop with a speed-up of up to 8x for the motion estimation module compared to the sequential version. Furthermore, the proposed algorithm is evaluated against some related proposals available in the literature, outperforming all of them in terms of time reduction as well as coding efficiency.

关键词： H.264/AVC Inter prediction GPU SmpUMHexagonS

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Rheology and processing of Ni based Nano-Composite Pastes for Electronic Assembly

Rheology and Processing of Ni based Nano-Composite Pastes fo...

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8th international conference on Composite Science and Technology

作者： Durairaja, R. Chiawea, L. Leong, Kau Chee Chu, Wong Mee Suan, Liang Meng UTAR Dept Mech & Mat Engn Kuala Lumpur 53300 Malaysia

ISBN: (纸本)9783037850596

Lead-free solder paste printing process accounts for majority of the assembly defects in the electronic manufacturing industry. In the stencil printing process, the solder paste must be able to withstand low and high shear rates, which results in continuous structural breakdown and build-up. the study investigates the effect of nickel additional to the thixotropic behaviour of lead-free Sn/Ag/Cu solder pastes using the structural kinetic model. A hysteresis loop test and constant shear test is utilized to investigate the thixotropic behaviour of the pastes using parallel plate rheometry in temperature 30 degrees C. In this study, the shear rates were increased from 0.01 s(-1) to 10s(-1) and the second curve was a result of decreasing shear rate from 10s(-1) to 0.01s(-1). For the constant shear test, the samples were subjected to two constant shear rates of 0.1s(-1) and 1s(-1). the constant shear rate test was designed to study the structural breakdown and build-up of the paste materials. From this investigation, hysteresis loop test was shown to be an effective test method to differentiate the extent of structural recovery in the solder pastes. the results of the structural parameter values obtained from the kinetic model showed a good correlation to the breakdown and build-up of the paste structure.

关键词： Rheology Lead-Free Solder Paste Nano-material and Nano-composite

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A research on controlling three-dimensional effect of the video frames obtained from stereo camera

A research on controlling three-dimensional effect of the vi...

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international conference on Information, Communications and Signal processing

作者： Jeehong Lee Kyu-yeol Chae Simon Ji LG Electronics Inc. Seoul South Korea

ISBN: (纸本)9781457700293

In recent years, 3D TVs and the 3D video contents such as movie, commercial film, or drama are widely exploited for many people. Due to these developments, many people will want to make the 3D contents with 3D cameras, and share these contents by uploading them to the UCC website. However, some people can experience the visual discomfort and fatigue when they are watching 3D video contents on the 3D TV. the reasons why this phenomenon is happened may be cross-talk, vertically-misaligned video contents obtained from the uncalibrated cameras, the collision of the accommodation and convergence, or the excessive three-dimensional effect. In our works, we mainly focused on controlling three-dimensional effect by modifying the convergence distance between the left and right camera. To achieve this, we analyzed the feature of the parallel and toe-in camera, and the relationship between the three-dimensional effect and convergence distances. From these experiments, we determined the type of the camera alignment and the proper convergence distance that satisfies the tradeoff between three-dimensional effect and visual fatigue. Also, to reduce visual fatigue and utilize the determined convergence distance, the proposed camera calibration method was used. this calibrated stereo camera was applied to our manufactured multimedia tablet, so that it could provide the comfortable three-dimensional effect.

关键词： Cameras three dimensional displays Convergence Stereo image processing Visualization Calibration Fatigue

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