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GSpTC: High-Performance Sparse Tensor Contraction on CPU-GPU Heterogeneous Systems

GSpTC: High-Performance Sparse Tensor Contraction on CPU-GPU...

引用

IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Guoqing Xiao Chuanghui Yin Yuedan Chen Mingxing Duan Kenli Li College of Computer Science and Electronic Engineering Hunan University Changsha China National Supercomputing Center in Changsha Changsha China Shenzhen Research Institute Hunan University Shenrhen China

Many fields of scientific simulation, such as chem-istry and condensed matter physics, are increasingly eschewing dense tensor contraction in favor of sparse tensor contraction. In this work, we centre around binary sparse tensor contraction (SpTC) which has the challenges of index matching and accumulation. To address and alleviate the above difficulties, we present GSpTC, an efficient element-wise SpTC framework on CPU-GPU heterogeneous systems. GSpTC first introduces a fine-grained index partition based on element-wise tensor con-traction, which facilitates efficient use of the parallel computing power of GPUs. In particular, GSpTC leverages multi-threading parallelism on GPUs for the contraction phase and merge phase, which greatly accelerates the computation phase in sparse tensor contraction. through evaluation of five datasets, we find that the proposed GSpTC achieves an average performance improvement of 74.32% compared to the previous state-of-the-art Sparta framework.

关键词： Tensors Instruction sets Graphics processing units parallel processing Indexes Chemical elements Physics

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A thermal-Aware Approach for DVFS-enabled Multi-core architectures

A Thermal-Aware Approach for DVFS-enabled Multi-core Archite...

引用

IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Javier Pérez Rodríguez Patrick Meumeu Yomsi Pavel Zaykov CISTER ISEP IPP Porto Portugal Honeywell Aerospace Brno Czech Republic

Reducing thermal dissipation is vital for modern multi-core architectures to meet increasing computational demands. In this paper, we consider non-preemptive periodic tasks at two importance levels - Safety-Critical tasks (SC-tasks) and Best-Effort tasks (BE-tasks) - executing on a homogeneous multi-core processor with DVFS capabilities under thermal-aware design. We assume that tasks are scheduled according to a fully partitioned Fixed-Task-Priority (FTP) scheduler. then, we propose two main contributions: (1) a new scheduling scheme, called NP-SafeSC, which reduces the responsiveness of SC-tasks as much as possible by procrastinating the execution of some BE-tasks; and (2) a new framework, called NP-thermCare, that allows controlling both processor activity and the triggering of the cooling mechanism so that timing and thermal requirements are met. We provide a thorough analysis of our solutions, validate the results and evaluate their performance against a real-world use-case and intensive simulations. Our approach shows a consistent improvement of NP-SafeSC over NP-COIN in the responsiveness of all SC-tasks on each core. In particular, the improvement for the SC-task with the lowest priority reaches 39.53% for the real-world use-case and 45.17% for the simulations.

关键词： Multicore processing Processor scheduling Cooling Process control Computer architecture thermal management Timing

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parallel processing and simulation: a panel discussion 82

Parallel processing and simulation: a panel discussion

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Proceedings of the 14th conference on Winter Simulation - Volume 2

作者： James G. Smith John C. Comfort J. Misra Ann Hayes George Fishman Office of Naval Research Arlington Virginia Florida International University Miami Florida University of Texas Austin Texas Los Alamos National Laboratory Los Alamos New Mexico University of North Carolina Chapel Hill North Carolina

Approaching rapidly on the horizon is a change to parallel architecture in digital computers that has the potential for multiplying the speed of execution achieved in serial architectures. the departure from serial operations provides rather obvious improvements in execution times for operations that are repetitive and that can be performed independently of each other. Such operations arise frequently in signal processing programs and in mathematical programming algorithms. Of interest to this conference is the impact of the new architectures on the practice of simulation - particularly simulations of large physical systems. A large number of questions can be raised (but few answered) on the impact of the new machines on simulation model designs, languages, data base manipulation, and other questions on the general utility of such machines for simulation problem solving. Moreover, it is likely that the new machines will influence the design of simulation experiments, random number generation, strategies for statistical iterations, sensitivity analyses, and variance reduction methods. Because of the interdisciplinary nature of these topics a dialog between simulation practitioners and computer technology developers will grow in importance. Several panelists, consisting of a mixture of simulation practitioners and computer scientists will describe their recent experiences in simulating systems on parallel computer configurations, highlighting efficiency comparisons and speculating on the general utility of such machines for simulation enterprises.

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Efficient Sparse Neural Networks Using Regularized Multi Block Sparsity Pattern on a GPU

Efficient Sparse Neural Networks Using Regularized Multi Blo...

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international conference on High Performance Computing

作者： Dharma Teja Vooturi Kishore Kothapalli Center for Security Theory and Algorithmic research (CSTAR) International Institute of Information Technology Hyderabad India

ISBN: (纸本)9781728145365

A large portion of the computation in sparse neural networks comprises of multiplying a sparse matrix with a dense matrix, denoted SDMM in this paper. the SDMM operation with an unstructured sparsity pattern cannot be efficiently processed on modern architectures such as GPUs due to irregularity in compute and memory accesses. However, efficient parallel algorithms on a GPU can be designed for SDMM when the sparsity pattern is more structured. thus, the run time performance of sparse neural networks on a GPU is dependent on the sparsity pattern present in the underlying matrix. In sparse neural networks obtained using pruning based approaches, the choice of sparsity pattern not only effects the run time, but also effects the accuracy of the task for which the neural network is trained for. Sparsity patterns which have a good run time performance on a GPU may not have a good accuracy and vice-versa. the real challenge then is to given a target architecture, identify a sparsity pattern, a storage format, and an algorithm for SDMM that leads to sparse neural networks which are efficient in both run time and accuracy. In this work, we propose a novel, structured, flexible, and generic sparsity pattern called the RMB (Regularized Multi Block) sparsity pattern, and an efficient storage format (CRMB), and a fast GPU algorithm for processing RMBMM (SDMM with the multiplicand having RMB sparsity pattern). Using the RMB sparsity pattern, we achieve better trade-offs between the accuracy, and the run time performance of sparse neural networks on a GPU when compared to commonly used sparsity patterns like unstructured, and block sparsity patterns.

关键词： Neural networks Sparse matrices Graphics processing units parallel algorithms Computer architecture Task analysis conferences

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ZeroVex: A Scalable and High-performance RISC-V Vector Processor Core for Embedded Systems

ZeroVex: A Scalable and High-performance RISC-V Vector Proce...

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international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Tenghao Zhao Zhaohui Ye Department of Automation Tsinghua University Beijing China

ISBN: (数字)9798350349634

ISBN: (纸本)9798350349641

this paper presents ZeroVex, a scalable and high-performance RISC-V vector processor core designed specifically for embedded devices. the architecture employs a portion of the RISC-V v1.0 vector ISA expansion specifically for edge machine learning inference. the ZeroVex microarchitecture consists of several similar lanes that operate concurrently. Every lane has vector function units and a portion of the vector register file, allowing for expandability. Furthermore, it utilizes multiple parallel execution strategies that depart from the traditional vector architecture to achieve a significant degree of parallelism. the experimental results show that ZeroVex, with a VLEN of 256-bit and 8 channels, achieves a speedup of 160x-235x and improves energy efficiency by 30x.

关键词： Performance evaluation Embedded systems Program processors Systems architecture Computer architecture parallel processing Vectors

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MPEG-4 Main Profile decoder partitioning with respect to bit stream processing

MPEG-4 Main Profile decoder partitioning with respect to bit...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： K.A. Jacob Institute for Integrated Circuits Munich University of Technology Munich Germany

the MPEG-4 object based profiles pose highly varying computational demands. To enable real-time and power efficient decoding of these profiles, parallelization of the algorithm is a necessity. At this, sensible system partitioning is of paramount concern in order to keep communication and synchronization overhead low. It is shown that especially the bit stream level decoding is considerably more complex than in earlier, frame based video coding standards. therefore, it is best executed on a dedicated unit. Based on the data dependencies between individual decoding operations, an interface between bit stream level and higher level decoding is derived which causes minimal synchronization overhead. An optimized software implementation of Main Profile bit stream level decoding shows that its computational demands for arbitrarily shaped Video Objects are 3.8-4.2 times as high as for frame based video. Under worst-case conditions 547.5MIPS are required for a Main@L2 decoder on a 32-bit MIPS RISC processor.

关键词： MPEG 4 Standard Decoding Streaming media Power dissipation Clocks Shape Voltage parallel processing Frequency synchronization Hardware

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A Novel parallel processing Architecture for Deblocking Filter in H.264 Using Vertical MB Filtering Order

A Novel Parallel Processing Architecture for Deblocking Filt...

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2006 8th international conference on Solid-State and Integrated Circuit Technology

作者： Yue-Xi Zhao An-Ping Jiang SOC Lab Department of microelectronicsPeking University

An efficient paraUel processing method for deblocking filter design in H.264 video coding standard is presented in this paper. In order to reduce the memory reference and make the intermediate data reused as soon as possible,an advanced filtering order is taken,and read/write operation on external memory is executed in parallel with filtering computation. Furthermore,preloading operation is taken to reduce complexity of memory structure,and vertical MB processing order is used for improving the efficiency of intermediate data *** a result,the processing cycles of the proposed architecture with single-port memory architecture is reduced by 80.5%compared with the advanced architecture of previous proposals.

关键词： AVC Filter A Novel parallel processing Architecture for Deblocking Filter in H.264 Using Vertical MB Filtering Order

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GPU-based Real-time Image Mosaicing for UAVs

GPU-based Real-time Image Mosaicing for UAVs

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international conference on Network and Information Systems for Computers (ICNISC)

作者： Feng Tian Yingbo Zhou Jialin Cheng Zhangwei Feng Jiawei Yu Guoxiang Ye Shechuan Duan Chengdu Aircraft Industrial (Group) Co. Ltd Chengdu China

ISBN: (纸本)9781665453523

Facing the problem of large amount of UAV image data, multiple redundancies and uneven quality, this paper proposes a GPU-based UAV real-time image mosaicing technology. First, the video stream data captured by the UAV is decoded to obtain frame images. then, for these large number of frames images, pre-processing such as cache frame extraction and geometric correction is performed to obtain high quality and low redundancy UAV images. Extracting image feature points and matching them by SIFT, SURF, etc., and screening matching points by RANSAC algorithm. Finally, based on the screened matching points, image fusion is performed to obtain the UAV mosaicing image. the overall process is parallel accelerated by GPU, which is more efficient and real-time. the mosaiced images can be tile-cut and stored in chunks to achieve fast sharing and efficient application of image data.

关键词： Matched filters Redundancy Graphics processing units Streaming media Feature extraction Real-time systems Reliability

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Hardware acceleration for sparse fourier image reconstruction

Hardware acceleration for sparse fourier image reconstructio...

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international conference on ASIC

作者： Quang Dinh Yoram Bresler Demmg Chen Department of Electrical and Computer Engineering University of Illinois Urbana-Champaign USA

Several supercomputer vendors now offer reconfigurable computing (RC) systems, combining general-purpose processors with fie Id-program m able gate arrays (FPGAs). the FPGAs can be configured as custom computing architectures for the computationally intensive parts of each application. In this paper we present an RC-based hardware accelerator for an important medical imaging algorithm: iterative sparse Fourier image reconstruction. We transform the algorithm to exploit massive parallelism available in the FPGA fabric. Our design allows different ways of chaining custom pipelined vector engines, so that different computations can be carried out without reconfiguration overhead. Actual runtime performance data show that we achieve up to 10 times speedup compared to the software-only version. the design is estimated to provide even more speedup on a next-generation RC platform.

关键词： Hardware Acceleration Image reconstruction Field programmable gate arrays Iterative algorithms Supercomputers Computer architecture Biomedical imaging parallel processing Fabrics

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Evaluation of MapReduce in a Large Cluster

Evaluation of MapReduce in a Large Cluster

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IEEE international conference on Cloud Computing, CLOUD

作者： Kamal Kc Chin-Jung Hsu Vincent W. Freeh North Carolina State University

MapReduce is a widely used framework that runs large scale data processing applications. However, there are very few systematic studies of MapReduce on large clusters and thus there is a lack of reference for expected behavior or issues while running applications in a large cluster. this paper describes our findings of running applications on Pivotal's Analytics Workbench, which consists of a 540-node Hadoop cluster. Our experience sheds light on how applications behave in a large-scale cluster. this paper discusses our experiences in three areas. the first describes scaling behavior of applications as the dataset size increases. the second discusses the appropriate settings for parallelism and overlap of map and reduce tasks. the third area discusses general observations. these areas have not been reported or studied previously. Our findings show that IO-intensive applications do not scale as data size increases and MapReduce applications require different amounts of parallelism and overlap to minimize completion time. Additionally, our observations also highlight the need for appropriate memory allocation for a MapReduce component and the importance of decreasing log file size.

关键词： Containers parallel processing throughput Benchmark testing Resource management Scalability Yarn

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