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Adaptive artificial neural network for robust estimation of parameters of asynchronous state

Adaptive artificial neural network for robust estimation of ...

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international conference on Environment and Electrical Engineering (EEEIC)

作者： Pawel Kostyla Tomasz Sikorski Zbigniew Waclawek Bogdan Leszkiewicz Department of Electrical Engineering Wroclaw University of Technology Wroclaw Poland Department of Regional Economy and Tourism in Jelenia Gora Wroclaw University of Economics Wroclaw Poland

In many applications, very fast methods are required for estimating of amplitudes of current signals distorted by noise. In this paper new parallel algorithms are proposed, which can be implemented by analogue adaptive circuits employing selected neural networks principles. algorithms based on the total least-squares (TLS) and the robust total least-squares (RTLS) criteria are developed and used to detection of asynchronous state of synchronous machines. the problems are formulated as optimization tasks and solved using the steepest descent continuous-time optimization algorithm. the corresponding architectures of analogue neuron-like adaptive processors are also shown. the developed networks are more robust against noise in the measured signal than other known neural network algorithms. the network based on the TLS criterion realizes the optimization process under the assumption that the signal model can also be deteriorated (frequency or sampling interval fluctuation and so forth). the TLS estimation effect is better and more reliable than the corresponding LS structure, when higher sampling frequency and a wider sampling window is applied. An asynchronous state of a synchronous machine may be identified through determining the amplitudes of particular components of stator's current provided that a constant slip value is assumed. Following a synchronism loss, this adopted value is assumed to be achieved and, for sure, exceeded. this work provides a description of artificial neural networks realising mentioned task of asynchronous state detection. Extensive computer simulations confirm the validity and performance of the proposed algorithms.

关键词： Stators Noise Robustness Estimation Synchronous machines Optimization Signal processing algorithms

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Scalable SubXPCA on a Distributed Platform Applied to Classification of Hyperspectral Images

Scalable SubXPCA on a Distributed Platform Applied to Classi...

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conference on Information and Communication Technology (CICT)

作者： Bogolu Rupa Atul Negi School of Computer and Information Sciences University of Hyderabad Department of Computer Science and Engineering Vardhaman College of Engineering Hyderabad Telangana India

ISBN: (数字)9798331531539

ISBN: (纸本)9798331531546

the exponential growth of technological advancements in satellite and airborne remote sensing is giving rise to large volumes of high-dimensional hyperspectral image data. Apache Spark is one of the most popular, extensively used and open-source distributed processing frameworks, which is proven effective in processing large volumes of remotely sensed hyperspectral images in a time-efficient manner. Open-source distributed processing frameworks have proven effective in processing large volumes of remotely sensed hyperspectral images quickly and efficiently. While computational power has been increasing, the rate of data accumulation is more than the processing capabilities. therefore, more efficient algorithms such as dimensionality reduction are needed to process and get accurate performance for the application. this paper proposes an efficient and parallel spectral dimensionality reduction approach based on feature partitioning principal component analysis called scalable SubXPCA. We implemented scalable SubXPCA on a spark cluster distributed environment. We compared scalable SubXPCA against other distributed feature partitioning and various non-feature partitioning dimensionality reduction methods. Our experiments on different real and synthetic datasets of hyperspectral images confirm that SubXPCA classification performance is not only better than its competitors but also that the running time of SubXPCA is better in distributed processing than serial processing. As the size of the hyperspectral image dataset increased, SubXPCA showed a speed up factor of 5.7× and more in the spark cluster compared to the serial version.

关键词： Dimensionality reduction Distributed processing Accuracy Satellites Partitioning algorithms Information and communication technology Sparks Hyperspectral imaging Principal component analysis Synthetic data

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A Lightweight CNN Design Based on Convolutional Autoencoder for Tomato Disease Identification

A Lightweight CNN Design Based on Convolutional Autoencoder ...

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international conference on Image and Signal processing and their Applications (ISPA)

作者： Ghania Boukhlifa Youcef Chibani Laboratoire d’Ingénierie des Systèmes Intelligents et Communicants (LISIC) Faculty of Electrical Engineering University of Science and Technology Houari Boumediene (USTHB) Algiers Algeria

ISBN: (数字)9798350309249

ISBN: (纸本)9798350309256

the accurate identification of tomato diseases is essential for improving crop yield and reducing economic losses in agriculture. Conventionally, the Convolutional Neural Network (CNN) is used as a model for feature extraction and data classification. However, the heavy computational requirements of most state of the art deep learning architectures based on this approach make them unsuitable for low-powered devices. In order to design a lighweight identification system for tomato disease, this paper proposes an alternative implementation by combining the Convolutional Autoencoder (CAE) for generating features with the CNN for classification. the CAE is used for encoding and decoding the data to determine the encoder’s effectiveness in preserving relevant features. then, the encoding layers are transferred to the CNN having fully connected layers for classification. the proposed framework is evaluated using the 10 classes of tomato leaf diseases available in the public Plant Village dataset. the experimental evaluation shows an outperformance comparatively to several heavy architectures with an accuracy of 99.13%. Additionally, It has low memory usage and fast inference time, making it suitable for deployment on resource-limited devices.

关键词： Training Analytical models Computer architecture Signal processing Encoding Time measurement Service-oriented architecture

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Design of a Web Vulnerability Scanning System for Multiple Drones Based on Python Data Link

Design of a Web Vulnerability Scanning System for Multiple D...

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2024 8th international conference on Electrical, Mechanical and Computer Engineering (ICEMCE)

作者： Jia Luo School of Mechanical Engineering Xijing University Xi’an Shaanxi China

ISBN: (数字)9798331506230

ISBN: (纸本)9798331506247

With the rapid development of technology, robotics is continuously making breakthroughs, and drones are increasingly used in various fields, bringing great convenience to human production and life. In the future, with the continuous advancement of technology and the expansion of application areas, drones will play a significant role in more fields. Against this backdrop, the cybersecurity issue of the drone system’s local area network becomes particularly important for the safe, stable, and sustainable development of drone technology. this article is dedicated to developing a vulnerability scanning system based on Python. the system comprehensively employs host scanning, port scanning, and specific Web vulnerability scanning to conduct a comprehensive and in-depth assessment of the cybersecurity of the drone local area network. the system aims to alert relevant network administrators to take preventive measures in a timely manner, ensuring the secure and stable operation of the system’s local area network.

关键词： Databases Area measurement Production parallel processing Computer security Sustainable development Local area networks Robots Drones Business

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[WIP] Unlocking Static Images for Training Event-driven Neural Networks

[WIP] Unlocking Static Images for Training Event-driven Neur...

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international conference on Event-based Control, Communication, and Signal processing (EBCCSP)

作者： Nicolò Carissimi Gaurvi Goyal Franco Di Pietro Chiara Bartolozzi Arren Glover Event-driven Perception for Robotics Italian Institute of Technology Genova Italy

ISBN: (数字)9781665453493

ISBN: (纸本)9781665453509

Event driven cameras have the potential to revolutionise the real-time visual sensory processing paradigm. these asynchronous sensors detect change in the environment with low latency and high dynamic range, allowing for orders of magnitude faster systems than the state of the art using intensity cameras. On the other hand, deep artificial neural networks have refashioned machine vision in the last decade, greatly expanding the reach of viable tasks, supported by the creation of many large scale image datasets. In this work, we present a modality to leverage these large scale datasets for the purpose of training off-the-shelf deep learning architectures and re-appropriating them for event-based tasks. To this end, we describe an event representation, EROS, and a method to convert images to an EROS-like representation such that image datasets can train neural networks for event driven applications.

关键词： Training Visualization Statistical analysis Machine vision Signal processing Cameras Sensor systems

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Analogic cellular PDE machines

Analogic cellular PDE machines

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international Joint conference on Neural Networks (IJCNN)

作者： C. Rekeczky I. Szatmari P. Foldesy T. Roska Computer and Automation Research Institute Hungary Hungarian Academy of Science Budapest Hungary Jedlik Laboratories Department of Information Technology Pázmány Péter Catholic University Budapest Hungary

this paper gives an overview on analogic cellular array architectures that can also be used to approximate partial differential equations (PDEs). Cellular arrays are massively parallel computing structures composed of cells placed on a regular grid. these cells interact locally an th e array can have both local and global dynamics. the software of this architecture is an analogic algorithm that builds on analog and logical spatio-temporal instructions of the underlying hardware, that is a locally connected cellular nonlinear network (CNN). Within this framework two classes of PDEs, motivated also by image processing methodologies will be discussed: (i) reaction-diffusion (local) types and (ii) contrast modification (global) types. It will be shown that based on cellular diffusion and wave-computing formulations these classes can be approximated on existing CNN Universal Machine (CNN-UM) chips. thus, the last generation of stored program topographic array microprocessors with integrated sensing and computing could also be viewed as the first prototypes of analogic cellular PDE machines implemented on silicon.

关键词： Computer architecture Cellular neural networks Partial differential equations parallel processing Software algorithms Hardware Cellular networks Image processing Turing machines Microprocessors

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Genetic-A* Algorithm-Based Routing for Continuous-Flow Microfluidic Biochip in Intelligent Digital Healthcare 18th

Genetic-A* Algorithm-Based Routing for Continuous-Flow Micr...

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18th international conference on Green, Pervasive, and Cloud Computing, GPC 2023

作者： Huang, Huichang Yang, Zhongliao Zhong, Jiayuan Xu, Li Dong, Chen Bao, Ruishen College of Computer and Data Science Fuzhou University Fuzhou350116 China College of Computer and Cyber Security Fujian Normal University Fuzhou350007 China Fujian Key Laboratory of Network Computing and Intelligent Information Processing Fuzhou University Fuzhou China

ISBN: (纸本)9789819998951

In the field of intelligent digital healthcare, Continuous-flow microfluidic biochip (CFMB) has become a research direction of widespread concern. CFMB integrates a large number of microvalves and large-scale microchannel networks into a single chip, enabling efficient execution of various biochemical protocols. However, as the scale of the chip increases, the routing task for CFMB becomes increasingly complex, and traditional manual routing is no longer sufficient to meet the requirements. therefore, this paper proposes an automatic routing framework for CFMB based on Genetic algorithm (GA) and A* algorithms. Specifically, we adopt a two-stage A* algorithm to design the routing between modules, using the routing results obtained from the A* algorithm as the basis for evaluating the quality of solutions in the GA algorithm. then, the GA algorithm is used to search for the optimal approximate solution in the solution space. Experimental results show that this method can reduce routing length and minimize routing crossings, thereby improving the parallel transmission speed of reagents on CFMB. this approach provides a feasible solution for large-scale automated routing of CFMB in the field of intelligent digital healthcare. © the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd 2024.

关键词： Genetic algorithms

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parallel Improved Schnorr-Euchner Enumeration SE++ for the CVP and SVP

Parallel Improved Schnorr-Euchner Enumeration SE++ for the C...

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Euromicro conference on parallel, Distributed and Network-Based processing

作者： Fábio Correia Artur Mariano Alberto Proença Christian Bischof Erik Agrell Technische Universität Darmstadt University of Minho Chalmers University of Technology

the Closest Vector Problem (CVP) and the Shortest Vector Problem (SVP) are prime problems in lattice-based cryptanalysis, since they underpin the security of many lattice-based cryptosystems. Despite the importance of these problems, there are only a few CVP-solvers publicly available, and their scalability was never studied. this paper presents a scalable implementation of an enumeration-based CVP-solver for multi-cores, which can be easily adapted to solve the SVP. In particular, it achieves super-linear speedups in some instances on up to 8 cores and almost linear speedups on 16 cores when solving the CVP on a 50-dimensional lattice. Our results show that enumeration-based CVP-solvers can be parallelized as effectively as enumeration-based solvers for the SVP, based on a comparison with a state of the art SVP-solver. In addition, we show that we can optimize the SVP variant of our solver in such a way that it becomes 35%-60% faster than the fastest enumeration-based SVP-solver to date.

关键词： Lattices Approximation algorithms Cryptography Scalability Decoding Matrix decomposition

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Implementation and Performance Evaluation of Novel Line Adder Architecture for Portable Systems : A Vedic Mathematics Approach

Implementation and Performance Evaluation of Novel Line Adde...

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IEEE Region 10 international conference TENCON

作者： Sudhanshu Janwadkar Rasika Dhavse Sardar Vallabhbhai National Institute of Technology Surat India

ISBN: (数字)9781728184555

ISBN: (纸本)9781728184562

In this paper, we propose design and implementation of novel line adder architecture capable of adding multiple addends in a single step. the architecture is derived based on addition algorithm from Shuddha system of vedic mathematics. the adder architecture is particularly suitable for a class of applications, such as FIR filter, where multiple operands are required to be added. the implementation is particularly suited for portable systems where area and power consumption are highly constrained. We then quantitatively compare proposed adder architecture against popular parallel-prefix adder architectures for different wordlengths (N = 4, 8, 16 and 32 bits). All the architectures are implemented on Genesys2 board (Xilinx part number xc7k325t-2ffg900c) using VHDL coding and Xilinx Vivado 2016.2 platform. Standard performance metrics such as FPGA device utilization (number of slices and logic LUTs), Power Consumption and Performance are considered for comparison. Results indicate that proposed vedic adder occupies 35.12 % lesser logic LUTs and 28.71 % lesser slices than any other adder architectures, under consideration, while at the same time, there is an improvement of 9.1 % in on-chip FPGA power consumption than all other adder architectures. the performance of vedic adder architecture draws parallel with that of fastest prefix adder being considered.

关键词： Adders Computer architecture Logic gates Mathematics Field programmable gate arrays Signal processing algorithms Power demand

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Accelerating Linear Algebra Kernels on a Massively parallel Reconfigurable Architecture

Accelerating Linear Algebra Kernels on a Massively Parallel ...

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IEEE international conference on Acoustics, Speech and Signal processing

作者： A. Soorishetty J. Zhou S. Pal D. Blaauw H. Kim T. Mudge R. Dreslinski C. Chakrabarti Arizona State University Tempe AZ University of Michigan Ann Arbor MI

ISBN: (数字)9781509066315

ISBN: (纸本)9781509066322

Much of the recent work on domain-specific architectures has focused on bridging the gap between performance/efficiency and programmability. We consider one such example architecture, Transformer, consisting of light-weight cores interconnected by caches and crossbars that supports run-time reconfiguration between shared and private cache mode operations. We present customized implementation of a select set of linear algebra kernels, namely, triangular matrix solver, LU decomposition, QR decomposition and matrix in-version, on Transformer. the performance of the kernel algorithms is evaluated with respect to execution time and energy efficiency. Our study shows that each kernel achieves high performance for a certain cache mode and that this cache mode can change when the matrix size changes, making a case for run-time reconfiguration.

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