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检索条件"任意字段=8th International Conference on Algorithms and Architectures for Parallel Processing"

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Research on Elastic Extension of Multi Type Resources for OpenMP Program

Research on Elastic Extension of Multi Type Resources for Op...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Junfeng Zhao Xuesong Gao Yuancong Li College of Computer Science Inner Mongolia University Hohhot China

OpenMP is one of the most popular programming models in the field of parallel computing, which is widely used in multi-threaded programming with shared memory. But with the continuous change of program computing scale, the problem of resource supply has become increasingly prominent. Making use of the cloud computing to dynamically provide resources for OpenMP program is a meaningful work. Based on the internal structure characteristics of OpenMP program, a flexible elastic resource allocation strategy is designed, and a load prediction method combining active and reactive prediction based on machine learning is proposed to realize the load prediction of OpenMP program. then, the fuzzy controller is used to coordinate the resources and infer the CPU and memory resources needed by the program in the next cycle. On this basis, the middleware OPEC is designed and implemented to realize the dynamic allocation of cloud resources during the operation of OpenMP program. Parsec, a benchmark test suite based on shared memory, is selected for experimental verification. the experimental results show that the solution proposed in this paper can dynamically provide a variety of resources for OpenMP program to meet program running requirements, effectively improve resource utilization efficiency and reduce program running costs.

关键词： Fuzzy logic Cloud computing Fuzzy control Machine learning Prediction methods Programming parallel processing

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PC-BNA: parallel Convolution Binary Neural Network Accelerator

PC-BNA: Parallel Convolution Binary Neural Network Accelerat...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Haihui Liu Yuang Zhang Xiangwei Zheng Mengxin Yu Baoxu An Xiaojie Liu Shandong Provincial Key Laboratory for Distributed Computer Software Novel Technology School of Information Science and Engineering Shandong Normal University Jinan China

Binary neural network (BNN) is widely used in speech recognition, image processing and other fields to save memory and speed up computing. However, the accuracy of the existing binarization scheme in the realistic dataset is obviously low, and the input layer uses 32-bit floating point to avoid excessive precision loss, which requires additional computing units and increases the computational burden. therefore, it is very important to improve the input layer, save computing resources and reduce precision loss. In this paper, we propose a parallel convolution binary neural network accelerator architecture (PC-BNA). Based on our proposed BNN model, we design an efficient field programmable gate array (FPGA) based accelerator. the input of the first layer is binarized, the traditional binary convolution layer is replaced by a parallel binary convolution, and the network building blocks are improved. the experimental results show that the proposed PC-BNA has higher accuracy and better performance on CIFAR-10. the image recognition accuracy is as high as 91.4%, which is superior to the state-of-art of the BNN accelerator. Compared to the state-of-the-art BNN model, when using the same model size, the use of look-up-table (LUT) saves 9.08%, and the digital signal processor (DSP) saves 27.7%. the results suggest that it is promising for PC-BNA in future high performance mobile artificial intelligence applications.

关键词： Performance evaluation Convolution Neural networks Digital signal processors Speech recognition Logic gates Mobile handsets

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Cloth Simulation Based on Local Adaptive Subdivision and Merging

Cloth Simulation Based on Local Adaptive Subdivision and Mer...

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the 8th international conference on Computer Supported Cooperative Work in Design(第八届计算机支持的协同工作设计国际会议)(CSCWD2004)

作者： JianZhen Lin Min Tang JinXiang Dong AI Institute State Key Laboratory of CAD&CGZheJiang UniversityHangZhou 310027

ISBN: (纸本)0780379411

To speed up cloth simulation while achieving realisticsimulation results, a local adaptive Catmull-Clarksubdivision is adopted in this paper. During the growingphase of cloth simulation, several new particles areadded to the system if the cloth grids collide with rigidobjects. the cloth grids are merged later when coarsegrids are sufficient. In this article, a mass-spring model isdeveloped for rectangle grids. Collision detection andresponse methods for local adaptive subdivision are alsodescribed. the exploitation of cache control instructionset and SIMD instructions allow us to achieve nearly100％ FPU utilization. the algorithm supports tradeoffsbetween simulation time and realistic results.

关键词： clothing fabrics digital simulation CAD product design production engineering computing cache storage instruction sets parallel processing cloth simulation local adaptive subdivision realistic simulation local adaptive Catmull-Clark subdivision cloth grid collision rigid objects cloth grid merging mass-spring model rectangle grids collision detection response methods cache control instruction set SIMD instructions FPU utilization computer aided design computer graphics

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A fully digital Background calibration technique for pipeline analog-to-digital converters

A fully digital Background calibration technique for pipelin...

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international conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON

作者： Ziaeddin Koozeh Kanani Jafar Sobhi Mousa Yousefi Ahmad Tahmasebi Department of Electrical Engineering University of Tabriz Tabriz Iran Sarab Branch Islamic Azad University Sarab Iran

this paper describes a new background calibration technique for pipeline analog-to-digital converters (ADCs). the new scheme utilizes an existing digital foreground calibration algorithm and extends it to work in background. the goal is to digitally calibrate the pipeline ADCs in the background without stopping the input conversion. In this method one additional stage connected in parallel to the stage under calibration and one cyclic ADC are used to accommodate the calibration. the extra stage and the cyclic ADC are only used during the calibration process. Sources of error in pipeline architectures and effects of error on residue plot of 1-bit per stage are identified and discussed. the digital background calibration accounts for capacitor mismatch, comparator offset, charge injection and finite op-amp gain. By applying proposed calibration to a 12 bit resolution pipeline ADC, maximum INL improved from 14 to 0.6 LSB, and maximum DNL improved from 26 to 0.8 LSB.

关键词： Calibration Pipelines Analog-digital conversion Voltage Operational amplifiers Topology Signal processing algorithms Capacitors Signal resolution Aging

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Implementing a Pickup and Delivery Problem with Time Windows algorithm on a GPU cluster

Implementing a Pickup and Delivery Problem with Time Windows...

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international conference on Computer Sciences and Convergence Information Technology (ICCIT)

作者： Geeratiya Srimool Putchong Uthayopas Juta Pichitlamkhen Department of Computer Engineering Faculty of Engineering Kasetsart University Bangkok Thailand Department of Industrial Engineering Faculty of Engineering Kasetsart University Bangkok Thailand

this work presents an implementation of a high speed Pickup and Delivery Problem with Time Window (PDPTW) problem using GPU cluster. this problem represents a class of a major logistic problem. the software implemented is tested on 8 nodes GPU cluster equipped with two of Tesla M2050 (448 cores) card on each node. the result shows a speedup of nearly 7 times for a small problem and 43 times using 4 nodes for a large problem. In the presentation, some factors that affect the performance will be discussed.

关键词： Graphics processing unit Instruction sets Vehicles parallel processing Clustering algorithms Handheld computers

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Template matching of aerial images using GPU

Template matching of aerial images using GPU

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international Bhurban conference on Applied Sciences & Technology, IBCAST

作者： Nabigha Nazneen Muhammad Shafiq Abdul Hameed KICSIT Rawalpindi Pakistan CESAT Islamabad Pakistan

During the last decade, processor architectures have emerged with hundreds and thousands of high speed processing cores in a single chip. these cores can work in parallel to share a work load for faster execution. this paper presents performance evaluations on such multicore and many-core devices by mapping a computationally expensive correlation kernel of a template matching process using various programming models. the work builds a base performance case by a sequential mapping of the algorithm on an Intel processor. In the second step, the performance of the algorithm is enhanced by parallel mapping of the kernel on a shared memory multicore machine using OpenMP programming model. Finally, the Normalized Cross-Correlation (NCC) kernel is scaled to map on a many-core K20 GPU using CUDA programming model. In all steps, the correctness of the implementation of algorithm is taken care by comparing computed data with reference results from a high level implementation in MATLAB. the performance results are presented with various optimization techniques for MATLAB, Sequential, OpenMP and CUDA based implementations. the results show that GPU based implementation achieves 32x and 5x speed-ups respectively to the base case and multicore implementations respectively. Moreover, using inter-block sub-sampling on an 8-bit 4000×4000 reference gray-scale image achieves the execution time upto 2.8sec with an error growth less than 20% for the selected templates of size 96×96.

关键词： Graphics processing units MATLAB Kernel Computational modeling Correlation Instruction sets Multicore processing

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Improved GAI-BP Detection for MIMO Systems Based on Message Post-processing

Improved GAI-BP Detection for MIMO Systems Based on Message ...

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international conference on ASIC

作者： Ruiyang Ji Wenyue Zhou Xiaosi Tan Xiaohu You Chuan Zhang Lab of Efficient Architectures for Digital-Communication and Signal-Processing (LEADS) National Mobile Communications Research Laboratory Southeast University Nanjing China Purple Mountain Laboratories Nanjing China

Multiple-input multiple-output serves as a key technique for modern wireless communication systems but brings big challenges in data detection. Belief propagation (BP) detection enjoys advances for its near-optimal error rate performance and strong robustness. However, the state-of-art BP detection algorithms suffer from either an exponentially increasing computational complexity or sub-optimal error rate performance. To address this issue, this paper proposes an efficient variant based on the real-domain GAI BP (RD-GAI-BP), called the improved RD-GAI-BP, achieving a better error rate performance at the expense of acceptable complexity increments. Numerical results demonstrate that, in the MIMO scenario with N r = 16, N t = 8 and 64-QAM modulation, the proposed improved RD-GAI-BP earns more than 2 dB SNR gains at the BER of 10 -3 when compared with the state-of-art RD-GAI-BP detection.

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A high effective algorithm of 32-bit multiply and MAC instructions' VLSI implementation with 32/spl times/8 multiplier-accumulator in DSP applications

A high effective algorithm of 32-bit multiply and MAC instru...

引用

international conference on Signal processing Proceedings (ICSP)

作者： Ze Tian Dun-shan Yu Yu-lin Qiu Microelectron. R&D Center Acad. Sinica Beijing China Institute of Microelectronics Peking University Beijing China Microelectronics R&D Center of Chinese Academy of Sciences Beijing China

ISBN: (纸本)0780374886

Multiply and multiply-accumulate (MAC) instructions (see ARM DDI0l00E, ARM Architecture Reference Manual) are fundamental instructions in DSP applications. In an embedded digital signal processing (DSP) core and high-performance enhanced DSP instruction processor core, the implementation of high-performance multiply and MAC instructions is very important. An algorithm of 32/spl times/32 multiply and MAC instructions' VLSI implementation with 32/spl times/8 multiplier-accumulator in DSP applications is presented. the 32/spl times/32 multiplication is achieved by 4 times 32/spl times/8 multiplication. the result of one 32/spl times/8 multiplication serves as a partial product of the next 32/spl times/8 operation; when the result of four such multiplications is accumulated, we get the result of 32/spl times/32. the 32/spl times/8 multiplication is only implemented by the hardware Booth multiplier. the algorithm of multiply and MAC instructions' implementation is the better trade-off between serial multiplier and parallel multiplier.

关键词： Very large scale integration Digital signal processing Signal processing algorithms Hardware Clocks Silicon Microelectronics Embedded system Research and development Speech processing

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FlexSFC: Flexible Resource Allocation and VNF parallelism for Improved SFC Placement

FlexSFC: Flexible Resource Allocation and VNF Parallelism fo...

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IEEE conference on Network Softwarization (NetSoft)

作者： Sagar Agarwal Venkatarami Reddy Chintapalli Bheemarjuna Reddy Tamma Indian Institute of Technology Hyderabad India

ISBN: (数字)9781665406949

ISBN: (纸本)9781665406956

To reduce the processing delay from the sequentially running virtual network functions (VNFs) in a service function chain (SFC), network function parallelism (NFP) is introduced that allows VNFs of the SFC to run in parallel. Existing NFP solutions only focused on improving parallelism benefits without paying much attention to resource utilization while deploying VNFs of SFCs. We take advantage of resource-delay dependency to propose a flexible and efficient parallelized SFC placement mechanism called FlexSFC which determines the optimal SFC placement while reducing resource usage and meeting end-to-end delay guarantees of the SFCs deployed. Initial results show that FlexSFC guarantees the end-to-end delay requirement with better resource utilization and SFC acceptance rate than the state-of-the-art approaches.

关键词： Service function chaining conferences parallel processing Dynamic scheduling Delays Resource management

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An adaptive value-based scheduling policy for multiprocessor real-time database systems

An adaptive value-based scheduling policy for multiprocessor...

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international Workshop on Database and Expert Systems Applications

作者： Shin-Mu Tseng Y.H. Chin Wei-Ping Yang LInstitute of Computer and Information Science National Chiao Tung University Hsinchu Taiwan Institute of Computer Science National Tsing Hua University Hsinchu Taiwan

In a real-time application, a transaction may be assigned a value to reflect the profit of completing the transaction before its deadline. Satisfying both goals of maximizing the totally obtained profit and minimizing the number of missed transactions at the same time is a challenge. the authors present an adaptive real-time scheduling policy named value-based processor allocation (VPA-k) for scheduling value-based transactions in a multiprocessor real-time database system. Using the VPA-k policy, the transactions with higher values are given higher priorities to execute first, while at most k percentage of total processors are dynamically allocated to execute the urgent transactions. through simulation experiments, VPA-k is shown to outperform other scheduling policies substantially in both maximizing the totally obtained profit and minimizing the number of missed transactions under various system environments.

关键词： Adaptive scheduling Real time systems Database systems Processor scheduling Scheduling algorithm parallel processing Multiprocessing systems Information science Computer science Application software

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