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检索条件"任意字段=8th International Conference on Algorithms and Architectures for Parallel Processing"

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A design of a GP-GPU based stream processor for an image processing

A design of a GP-GPU based stream processor for an image pro...

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international conference on Telecommunications and Signal processing (TSP)

作者： Kwang Yeob Lee Gyutaek Kyung Tae Ryong Park Jae Chang Kwak Yong Seo Koo Department of Computer Engineering Seokyeong University Seoul Korea NEXTCHIP co. Ltd Korea Department of Computer Science Seokyeong University Seoul Korea Department of Electronics Engineering Dankook University Korea

ISBN: (纸本)9781479984992

Mobile devices provide a more realistic image processing and various high spec features to satisfy users. So, mobile devices have been developing in the direction of computing acceleration by using a strong parallelism of GP-GPU processing. In this paper, a GP-GPU architecture is proposed based on stream processing architecture which has the advantage of high parallelism to enhance the image processing capability. the proposed GP-GPU architecture consists of 8 stream processors and has multi-banked cache memory structure. the results of verification shows that the proposed stream processor improves the performance of the integral image generation : 24.5%, 3×3 Gaussian filer mask : 4.7%, 5×5 Gaussian filter mask : 1.3% in comparison with ARM Cortex-A15 quad core.

关键词： Instruction sets Computer architecture parallel processing Image processing Cache memory Indexes Filtering algorithms

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An Overview of YOLO-Based Helmet Detection: Modifications and Advancements

An Overview of YOLO-Based Helmet Detection: Modifications an...

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international conference on Imaging, Signal processing and Communication (ICISPC)

作者： Seba Al Mokdad Manar Abu Talib Simon Zerisenay Ghebremeskel Fouad Lamghari Shaher Bano Mirza Ali Bou Nassif Department of Computer Science University of Sharjah United Arab Emirates Artificial Intelligence Department Fujairah Research Centre Fujairah United Arab Emirates Research Department Fujairah Research Centre Fujairah United Arab Emirates

ISBN: (数字)9798350367157

ISBN: (纸本)9798350367164

Small objects detection is a major challenge in computer vision and one well-known example of this is helmet detection. Helmets have a small size, which limits typical YOLO (You Only Look Once) object detection models from efficiently detecting them. Recent studies have focused on modifying several YOLO architectures to propose a solution to this problem. this study provides a comprehensive evaluation of novel solutions that address the helmet detection problem which include modifying multiple YOLO versions. A comprehensive examination of 53 research publications, which were published the period between 2019 to 2023, out of which 30 were included investigates the contributions in terms of model modifications, datasets used for evaluation, loss function optimization, and resulting performance measures. Several YOLO versions are addressed including YOLOv3, YOLOv4, YOLOv5, YOLOv7, and YOLOX. the studies discuss various modifications to YOLO including architecture modifications, integration of attention mechanisms, addition of detection scales, optimization and regularization techniques, loss function Improvements and anchor box optimization. the findings provide insight into the evolution of helmet detection algorithms within the YOLO architecture and how these modifications helped in addressing the problem of small objects detection. this review aims to provide academics and practitioners with significant insights into cutting-edge techniques for overcoming the challenges of identifying small objects as helmets.

关键词： YOLO Head Reviews Imaging Computer architecture Signal processing Loss measurement

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the Ni1000: high speed parallel VLSI for implementing multilayer perceptrons 94

The Ni1000: high speed parallel VLSI for implementing multil...

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Proceedings of the 8th international conference on Neural Information processing Systems

作者： Michael P. Perrone Leon N. Cooper Thomas J. Watson Research Center Yorktown Heights NY Institute for Brain and Neural Systems Brown University Providence RI

In this paper we present a new version of the standard multilayer perceptron (MLP) algorithm for the state-of-the-art in neural network VLSI implementations: the Intel Ni1000. this new version of the MLP uses a fundamental property of high dimensional spaces which allows the l2-norm to be accurately approximated by the l1-norm. this approach enables the standard MLP to utilize the parallel architecture of the Ni1000 to achieve on the order of 40000, 256-dimensional classifications per second.

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ParaLaR: A parallel FPGA router based on Lagrangian relaxation

ParaLaR: A parallel FPGA router based on Lagrangian relaxati...

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international conference on Field Programmable Logic and Applications

作者： Chin Hau Hoo Akash Kumar Yajun Ha Department of Electrical and Computer Engineering National University of Singapore Singapore

Routing of nets is one of the most time consuming steps in the FPGA design flow. While existing works have described ways of accelerating the process through parallelization, they are not scalable. In this paper, we propose a scalable way of parallelizing the routing algorithm through Lagrangian relaxation. the FPGA routing problem is formulated as a linear programming problem, and the channel width constraints, which limit the amount of parallelism, are relaxed by incorporating them into the objective function. the result of the relaxation yields independent sub-problems that we solve using minimum Steiner tree algorithms. Our approach outperforms the state-of-the-art FPGA parallel router by producing an average self-relative speedup of 7.05X with 8 threads, reduces the total wire length by 22.4% on average and has similar channel width requirements as VPR, albeit at the cost of 7.5% longer critical path. Another advantage of our algorithm is that the number of threads and the order in which the nets are routed has totally no impact on the quality of result.

关键词： Routing Steiner trees Field programmable gate arrays Algorithm design and analysis Linear programming Wires parallel processing

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Wildfire Detection in Video Images Using Deep Learning and HMM for Early Fire Notification System

Wildfire Detection in Video Images Using Deep Learning and H...

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IIAI international conference on Advanced Applied Informatics (IIAIAAI)

作者： Kuo-Ming Hung Li-Ming Chen Jin-An Wu Dept. of Information Management Kainan University Taoyuan Taiwan(R.O.C.) Dept. of Elec. and Computer Engineering Tamkang University New Taipei Taiwan(R.O.C.)

ISBN: (纸本)9781728126289

Conflagration is disaster that strongly influence environmental ecology and lives. In building, sensors are sufficient to support notification and evacuation. In contrast, the outdoor fire notification is supported via image fire detection. For wildfire notification and assistance in rescue, many researches extract fire characteristic from digital image to detect fire. However, the false alarm of detection system happens when it find the little flame can be extinguished itself with time. In case of false alarm often happens, the rescuer may neglect it and lose the first opportunity to rescue in mission. In this paper, we propose a system that combine deep learning and hidden markov model (HMM) in order to reduce frequency of false alarm. Our proposed system defines the status transformation of images/frames. Afterwards, the relationship of status transition is employed to notification classes. As experimental result, the fire detection rate of all deep learning architectures can achieve more than 96%. And our proposed system can also reduce up to 88.54% false alarm rate to decrease the waste of emergency manpower effectively.

关键词： emergency management fires hidden Markov models learning (artificial intelligence) neural nets object detection video signal processing Hidden Markov models Video signal processing Neural network Fire crisis management Object detection False alarms notification Emergency Services False-positives NOTIFICATION SYSTEMS fire detection

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Low-power high-order band-pass active-RC allpole filters using a "lossy" LP-BP transformation

Low-power high-order band-pass active-RC allpole filters usi...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： D. Jurisic N. Mijat G.S. Moschytz Department of Electronic Systems and Information Processing University of Zagreb Zagreb Croatia Signal and Information Processing Laboratory (ISI) Swiss Federal Institute of Technology Zurich Switzerland

the design procedure for high-order single amplifier BP filters is presented. A method for the design of 2/sup nd/- and 4/sup th/-order band-pass (BP) active-RC filters using a modified low-pass to band-pass (LP-BP) frequency transformation, has already been presented in previous works. It showed that a BP filter could be realized simply by the substitution of resistors and capacitors of the ladder in a low-pass (LP) prototype filter, by serial and parallel RC circuits. Such a substitution results from a so-called "lossy" LP-BP transformation. In this paper, the design procedure is extended to higher-order BP filters, such as 6th- and 8th-order. the design procedure is simple, and the closed-form design equations are presented. Furthermore, it is shown that "impedance tapering" decreases sensitivities to component tolerances for the LP prototype, as well as for the resulting BP filter. Schoeffler's sensitivity measure is used for the sensitivity analysis.

关键词： Band pass filters Prototypes Design methodology Frequency Resistors Capacitors Low pass filters Circuits Equations Impedance

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VeriAbs : Verification by Abstraction and Test Generation

VeriAbs : Verification by Abstraction and Test Generation

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IEEE international conference on Automated Software Engineering (ASE)

作者： Mohammad Afzal A. Asia Avriti Chauhan Bharti Chimdyalwar Priyanka Darke Advaita Datar Shrawan Kumar R. Venkatesh Tata Research Development and Design Center Pune India

Verification of programs continues to be a challenge and no single known technique succeeds on all programs. In this paper we present VeriAbs, a reachability verifier for C programs that incorporates a portfolio of techniques implemented as four strategies, where each strategy is a set of techniques applied in a specific sequence. It selects a strategy based on the kind of loops in the program. We analysed the effectiveness of the implemented strategies on the 3831 verification tasks from the ReachSafety category of the 8th international Competition on Software Verification (SV-COMP) 2019 and found that although classic techniques - explicit state model checking and bounded model checking, succeed on a majority of the programs, a wide range of further techniques are required to analyse the rest. A screencast of the tool is available at https://***/Hzh3PPiODwk.

关键词： Model checking Portfolios Tools Fuzzing Scalability Diversity reception parallel processing

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Novel Word-Level Sequential Scheme and parallel Architecture For Bit Plane Coding in JPEG2000

Novel Word-Level Sequential Scheme and Parallel Architecture...

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2006 8th international conference on Signal processing

作者： Zhirong Gao Chengyi Xiong Department of Computer Science Wuhan University of Science & Engineering College of Electronic Information Engineering South-Center University for Nationalities

this paper presented an improved word -level sequential scheme and parallel architecture for bit plane coding of EBCOT used in JPEG *** bit plane coding adopted by EBCOT is divided into two stages:coding pass prediction and context formation,which work in parallel and pipelined. Word-level and sequential bit plane coding could be achieved that coefficient bits modelling in different bit plane are performed concurrently and,all three passes coding included in each bit plane are completed in one *** result demonstrates that the proposed architecture could efficiently reduce hardware complexity,compared to the up-to -date design.

关键词： bit plane coding word-level sequential pipeline parallel.

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Spatial Constrained and Candidate Expanded parallel Matching for Ultra-Low Delay Camera Pose Estimation

Spatial Constrained and Candidate Expanded Parallel Matching...

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international conference on Imaging, Signal processing and Communication (ICISPC)

作者： Tengxiao Sun Yuan Li Tingting Hu Ryuji Fuchikami Wei Wang Takeshi Ikenaga Graduate School of Information Production and Systems Waseda University Kitakyushu Japan Research and Development Division Panasonic Connect Co. Ltd. Osaka Japan

ISBN: (数字)9798350367157

ISBN: (纸本)9798350367164

In fields like robotics and factory automation (FA), an ultra-low delay vision system has emerged as a critical tool. this system processes videos at an astonishing 1000 frames per second (fps), with each frame being processed within 1 millisecond (1-ms). Camera pose estimation plays a crucial role by providing real-time and accurate spatial information, enabling rapid response and precise control of production processes in such systems. Existing works mainly focus on general purpose use (60 fps) while less of the focus on specific use (1000 fps). this paper proposed an ultra-low delay camera pose estimation method designed to meet the stringent requirements of modern $F A$ systems. the spatial constrained and candidate expanded parallel matching is proposed for accelerating 3D-2D matching process. Spatial constrain utilizes the tiny movements between adjacent frames to shrink the search range to decrease the probability of matching conflicts. And candidate expansion increases the candidate matching points to guarantee the quality of matching between 2D and 3D spaces, which increases parallelism and enhances efficiency of the 3D-2D matching process. Experiments are conducted using a 1000 fps camera with resolution of $640 \times 360$. the proposed method demonstrated robust performance across horizontal, vertical, and random camera movements, achieving an average Relative Pose Error (RPE) of 0.5 cm for translation and 0.4 degrees for rotation respectively.

关键词： three-dimensional displays Accuracy Pose estimation Signal processing algorithms Cameras Delays Complexity theory

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MPSoC architecture for H.264/AVC intra prediction chain on SoCLiB platform and FPGA technology

MPSoC architecture for H.264/AVC intra prediction chain on S...

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international conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA)

作者： N. Belhadj M. Turki Z. Marrakchi M. Ali Ben Ayed N. Masmoudi H. Mehrez Laboratory of Electronics and Technology of Information from the National Engineering University of Sfax Tunisia Laboratory of Computer Sciences LIP6 University of Pierre and Marie Curie Paris France

Multiprocessor System on Chip (MPSoC) technology can present an interesting solution to reduce the computational time of complex applications. Execute the H.264/AVC encoder on MPSoC architecture, is becoming an interesting point of research that can mitigate its algorithmic complexity and to resolve the real time constraints. In this paper, we present an efficient MPSoC architecture for the intra prediction process which is an important module of the H.264/AVC video encoder, using Data Level parallelism (DLP) partitioning. this architecture is tested on an open platform for MPSoC architectures virtual designing (SoCLiB), and validated on FPGA technology. Experimental results show a gain of 74% in term of encoding speed when using four processors for coding a High Definition Video sequence (HDV) compared to uni-processor architecture.

关键词： Computer architecture Program processors Video coding Encoding Field programmable gate arrays parallel processing Partitioning algorithms

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