检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

2,760 篇 会议
56 册 图书
48 篇 期刊文献

馆藏范围

2,862 篇 电子文献
2 种 纸本馆藏

日期分布

学科分类号

2,010 篇 工学
- 1,777 篇 计算机科学与技术...
- 939 篇 软件工程
- 294 篇 信息与通信工程
- 291 篇 电气工程
- 245 篇 电子科学与技术（可...
- 94 篇 控制科学与工程
- 52 篇 机械工程
- 49 篇 生物工程
- 44 篇 光学工程
- 41 篇 生物医学工程（可授...
- 36 篇 仪器科学与技术
- 27 篇 动力工程及工程热...
- 27 篇 化学工程与技术
- 21 篇 土木工程
- 20 篇 力学（可授工学、理...
- 19 篇 材料科学与工程（可...
- 18 篇 建筑学
539 篇 理学
- 385 篇 数学
- 105 篇 物理学
- 55 篇 生物学
- 48 篇 系统科学
- 32 篇 统计学（可授理学、...
- 31 篇 化学
197 篇 管理学
- 121 篇 管理科学与工程(可...
- 81 篇 图书情报与档案管...
- 56 篇 工商管理
50 篇 医学
- 41 篇 临床医学
- 16 篇 基础医学(可授医学...
19 篇 文学
17 篇 经济学
- 17 篇 应用经济学
15 篇 法学
- 14 篇 社会学
11 篇 农学
4 篇 教育学
3 篇 军事学

主题

340 篇 parallel process...
200 篇 parallel process...
190 篇 computer archite...
157 篇 graphics process...
153 篇 parallel archite...
112 篇 parallel algorit...
107 篇 graphics process...
106 篇 hardware
86 篇 image processing
78 篇 computational mo...
73 篇 signal processin...
70 篇 concurrent compu...
66 篇 instruction sets
65 篇 algorithm design...
65 篇 multicore proces...
63 篇 field programmab...
60 篇 parallel program...
59 篇 parallel computi...
53 篇 gpu
48 篇 digital signal p...

机构

10 篇 natl univ def te...
8 篇 college of compu...
6 篇 hosei univ dept ...
6 篇 college of compu...
5 篇 univ aizu dept c...
5 篇 national univers...
5 篇 natl univ def te...
5 篇 city university ...
5 篇 science and tech...
4 篇 chinese acad sci...
4 篇 school of comput...
4 篇 carleton univ sc...
4 篇 univ chinese aca...
4 篇 school of comput...
4 篇 charles univ pra...
4 篇 department of co...
4 篇 school of comput...
4 篇 hainan internati...
4 篇 purple mountain ...
4 篇 department of co...

作者

10 篇 liu jie
9 篇 jack dongarra
8 篇 roman wyrzykowsk...
7 篇 wang qinglin
7 篇 konrad karczewsk...
7 篇 quintana-orti en...
6 篇 gepner pawel
6 篇 peng shietung
6 篇 li kuan-ching
6 篇 li yamin
6 篇 chu wanming
6 篇 prasanna viktor ...
6 篇 rothermel kurt
6 篇 yang chao-tung
5 篇 dongarra jack
5 篇 olas tomasz
5 篇 hannig frank
5 篇 wanlei zhou
5 篇 qian depei
5 篇 ewa deelman

语言

2,839 篇 英文
14 篇 其他
13 篇 中文
1 篇 俄文

检索条件"任意字段=8th International Conference on Algorithms and Architectures for Parallel Processing"

共 2864 条记录，以下是2791-2800 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Dynamic Communication-Efficient parallel Sorting on SMPs

Dynamic Communication-Efficient Parallel Sorting on SMPs

引用

IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Tipraporn thanakulwarapas Jeeraporn Werapun Department of Computer Science Faculty of Science King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand

this paper proposes a dynamic communication-efficient pattern and introduces a new efficient data-exchange process in parallel sorting, called the DCES (Dynamic Communication-Efficient parallel Sorting) algorithm, to improve the communication time. In this approach, we present the dynamic communication pattern by using a ldquoBroadcast-Checkerrdquo table, which can reduce total iterations to one iteration (in best case), or 2, 3, ..., or up to log2P(log2P+1)/2 (in worst case), while total (static) iterations of the recently study are fixed = log2P(log2P+1)/2. Finally to evaluate the sorting performance, we implemented our DCES algorithm on the SGI Origin2000. Our investigated experimental results have been compared to those of the best of existing algorithms (LBM: Load Balanced Merge sort). In the experiments, the proposed DCES algorithm yielded the improved results over those of the LBM algorithm at least 24% on the system of size P = 4 and at least 34% on the system of size P = 8.

关键词： Sorting High performance computing Computer science Broadcasting Concurrent computing Merging Information retrieval Graph theory Computational geometry Image processing

来源：评论

学校读者我要写书评

暂无评论

Efficient parallel Intra-prediction Mode Selection Scheme for 4x4 Blocks in H.264

Efficient Parallel Intra-prediction Mode Selection Scheme fo...

引用

international conference on Intelligent Computation Technology and Automation, ICICTA

作者： Liangbao Jiao Jing Zhou Rui Chen School of Communications engineering Nanjing Institute of Technology Nanjing China College of Communication and Information System Nanjing University of Posts and Telecommunications Nanjing China

An intra-prediction mode with 4×4 block and 16×16 block sizes for luma component and 8×8 block size for chroma component is used in H.264 to improve the rate-distortion performance. However, the computational complexity of H.264 encoder is drastically increased due to the various intraprediction modes. Recently efficient hardware architectures were proposed for the fast execution of H.264/AVC intraprediction mode selection. this paper proposes an efficient pipelining method for the 4×4 blocks intra-prediction mode selection. In particular, we exploit the GPU's streaming architecture at 4 × 4 intra-prediction mode selection in H.264/AVC and we develop a special strategy including instruction optimization and taking full advantage of shared memory to further exploit the fine-grained parallelism of GPUs. Experimental results up to about 3×speedup of our GPU-based algorithms over the implementations on sequential CPUs.

关键词： Graphics processing unit Instruction sets Optimization Algorithm design and analysis System-on-a-chip Programming Automatic voltage control

来源：评论

学校读者我要写书评

暂无评论

Design and Timing Analysis of 32 Bit Floating Point Pipelined Multiplier

Design and Timing Analysis of 32 Bit Floating Point Pipeline...

引用

international conference on Computation System and Information Technology for Sustainable Solutions (CSITSS)

作者： Surabhi A S Amogh Yogesh Naragund Sahana M S Keerthana V Shylashree N Department of Electronics and Communication RV College of Engineering Bangalore India

ISBN: (数字)9798331505462

ISBN: (纸本)9798331505479

the pipelined multiplier is designed to handle 32-bit floating-point operands and employs a pipelined architecture for improved performance. this paper examines the Verilog implementation and timing analysis of pipelined multipliers using Vivado Tool, specifically focusing on the assessment of timing slack. through separate evaluations, it discusses instances where timing constraints are met and violated for multiplier design. the design employs LUTs primarily for logic operations, with 82 Slice Registers for state storage and pipelining. the total on chip power consumption is of 0.119 W. Positive slack of 2.546 ns is recorded and by analyzing timing slack, the paper provides valuable insights into the timing performance of both architectures, aiding in understanding their reliability and potential optimization avenues.

关键词： Power demand Computer architecture Reliability engineering Timing Table lookup Registers Logic Hardware design languages Optimization Pipeline processing

来源：评论

学校读者我要写书评

暂无评论

Reliability and Modelability Advantages of Distributed Switching for Reconfigurable 2D Processor Arrays

Reliability and Modelability Advantages of Distributed Switc...

引用

international conference and Workshop on Computing and Communication (IEMCON)

作者： Behrooz Parhami University of California Santa Barbara CA USA

ISBN: (数字)9781728184166

ISBN: (纸本)9781728184173

Processor arrays have been used, either as the main computation engine or as special-purpose adjuncts, for a variety of applications requiring very high performance. As the size of such an array increases, the possibility of processor malfunctions, leading to loss of computational capabilities, can no longer be ignored. While many switching architectures and reconfiguration algorithms have been proposed for building processor arrays, modeling of their reliability has been inadequately addressed. In this paper, I study differences between 2D processor arrays with centralized and distributed switching, pointing to advantages of the latter in terms of reliability, regularity, modularity, and VLSI realizability. As important side results, I formulate the notions of reliability inversion (a less reliable system prevailing over a more reliable one due to modeling uncertainties) and modelability (the property of a system that makes it possible to derive tight reliability bounds, thus making reliability inversion less likely).

关键词： Uncertainty Systematics Two dimensional displays Switches parallel processing Very large scale integration Reliability engineering

来源：评论

学校读者我要写书评

暂无评论

A Locality-Preserving Write Buffer Design for Page-Mapping Multichannel SSDs

A Locality-Preserving Write Buffer Design for Page-Mapping M...

引用

IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Sheng Min Huang Li Pin Chang Department of Computer Science National Chiao-Tung University Taiwan

ISBN: (纸本)9781479961245

Advanced SSDs employ a RAM-based write buffer to improve their write performance. the buffer intentionally delays write requests in order to reduce flash write traffic and reorders them to minimize the cost of garbage collection. this work presents a novel buffer algorithm for page-mapping multichannel SSDs. We propose grouping temporally or spatially correlated buffer pages and writing these grouped buffer pages to the same flash block. this strategy dramatically increases the probability of bulk data invalidations in flash blocks. In multichannel architectures, channels are assigned to their own groups of buffer pages for writing, and so channel striping does not divide a group of correlated buffer pages into small pieces. We have conducted simulations and experiments using a SSD simulator and a real SSD platform, respectively. Our results show that our design greatly outperforms existing buffer algorithms.

关键词： Ash Writing Buffer storage Algorithm design and analysis parallel processing Heuristic algorithms Correlation

来源：评论

学校读者我要写书评

暂无评论

40 Gb/s FPGA implementation of a reduced complexity volterra DFE for DQPSK optical links

40 Gb/s FPGA implementation of a reduced complexity volterra...

引用

international conference on Transparent Optical Networks

作者： M. Nanou A. Emeretlis C. Politi G. theodoridis K. Georgoulakis G.O. Glentis Department of Informatics and Telecommunications University of Peloponnese Tripoli Greece Department of Electrical and Computer Engineering University of Patras Patras Greece

A low complexity MIMO Volterra Decision Feedback Equalizers (VDFE) for optical transmission systems employing NRZ-DQPSK signalling is proposed. Based on a comparative study performed by means of simulations, it is proved that the proposed equalizers maintain the required efficiency in terms of BER, achieving significant reduction in terms of complexity. Also, suitable architectures for high-speed FPGA implementations are presented. A 8-input 2-output low complexity VDFE involving three taps feed-forward filtering and two taps backward filtering was implemented on a single state-of-the-art FPGA. the target rate of 40 Gb/s is achieved by applying extensive pipelining and parallelism and fully exploiting specific FPGA features.

关键词： Field programmable gate arrays Complexity theory Optical fibers Optical filters Equalizers Optical fiber communication parallel processing

来源：评论

学校读者我要写书评

暂无评论

Effective and Unsupervised Fractal-Based Feature Selection for Very Large Datasets: Removing Linear and Non-linear Attribute Correlations

Effective and Unsupervised Fractal-Based Feature Selection f...

引用

IEEE international conference on Data Mining Workshops (ICDM Workshops)

作者： Antonio C. Fraideinberze José F. Rodrigues Robson L. F. Cordeiro Computer Sciences Department University of São Paulo São Carlos Brazil

ISBN: (纸本)9781509059119

Given a very large dataset of moderate-to-high dimensionality, how to mine useful patterns from it? In such cases, dimensionality reduction is essential to overcome the "curse of dimensionality". Although there exist algorithms to reduce the dimensionality of Big Data, unfortunately, they all fail to identify/eliminate non-linear correlations between attributes. this paper tackles the problem by exploring concepts of the Fractal theory and massive parallel processing to present Curl-Remover, a novel dimensionality reduction technique for very large datasets. Our contributions are: Curl-Remover eliminates linear and non-linear attribute correlations as well as irrelevant ones, it is unsupervised and suits for analytical tasks in general - not only classification, it presents linear scale-up, it does not require the user to guess the number of attributes to be removed, and, it preserves the attributes' semantics. We performed experiments on synthetic and real data spanning up to 1.1 billion points and Curl-Remover outperformed a PCA-based algorithm, being up to 8% more accurate.

关键词： Fractals Correlation Principal component analysis Big data Complexity theory Data mining parallel processing

来源：评论

学校读者我要写书评

暂无评论

X-Ray Computed Tomography Applied to Objects of Cultural Heritage: Porting and Testing the Filtered Back-Projection Reconstruction Algorithm on Low Power Systems-on-Chip

X-Ray Computed Tomography Applied to Objects of Cultural Her...

引用

Euromicro conference on parallel, Distributed and Network-Based processing

作者： Elena Corni Lucia Morganti Maria Pia Morigi Rosa Brancaccio Matteo Bettuzzi Giuseppe Levi Eva Peccenini Daniele Cesini Andrea Ferraro Department of Physics and Astronomy University of Bologna Bologna Italy Bologna Section Italian Institute for Nuclear Physics (INFN) Bologna Italy Enrico Fermi Center for Study and Research Roma Italy CNAF Section Italian Institute for Nuclear Physics (INFN) Bologna Italy

the embedded and high-performance computing (HPC) sectors, that in the past were completely separated, are now somehow converging under the pressure of two driving forces: the release of less power consuming server processors and the increased performance of the new low power Systems-on-Chip (SoCs) developed to meet the requirements of the demanding mobile market. this convergence allows the porting to low power embedded architectures of applications that were originally confined to traditional HPC systems. In this paper, we present our experience of porting the Filtered Back-projection Algorithm to a low power, low cost system-on-chip, the NVIDIA Tegra K1, which is based on a quad core ARM CPU and on a NVIDIA Kepler GPU. this Filtered Back-projection Algorithm is heavily used in 3D Tomography reconstruction software. the porting has been done exploiting various programming languages (i.e. OpenMP, CUDA) and multiple versions of the application have been developed to exploit both the SoC CPU and GPU. the performances have been measured in terms of 2D slices (of a 3D volume) reconstructed per time unit and per energy unit. the results obtained with all the developed versions are reported and compared with those obtained on a typical x86 HPC node accelerated with a recent NVIDIA GPU. the best performances are achieved combining the OpenMP version and the CUDA version of the algorithm. In particular, we discovered that only three Jetson TK1 boards, equipped with Giga Ethernet interconnections, allow to reconstruct as many images per time unit as a traditional server, using one order of magnitude less energy. the results of this work can be applied for instance to the construction of an energy-efficient computing system of a portable tomographic apparatus.

关键词： Graphics processing units Image reconstruction Computer architecture Filtering algorithms Computed tomography Radiography

来源：评论

学校读者我要写书评

暂无评论

Accelerating the iterative linear solver for reservoir simulation on multicore architectures

Accelerating the iterative linear solver for reservoir simul...

引用

international conference on parallel and Distributed Systems (ICPADS)

作者： Wei Wu Xiang Li Lei He Dongxiao Zhang Electrical Engineering Dept. University of California Los Angeles Los Angeles United States Dept. of Energy and Resources Engineering Peking University Beijing China

Modern petroleum reservoir simulation serves as a primary tool for quantitatively managing reservoir production and planning new fields. It involves repeatedly solving the Jacobian of a set of strong nonlinear partial differential equations governing the mass and energy conduction and conservation. Most of the existing reservoir simulators adopt iterative solver with multiple stages of preconditioners, in which the incomplete LU (ILU) factorization is an outstanding universal smoother. However, it turns out that when the degree of freedom of each grid grows, ILU usually becomes the bottleneck of the solver. Moreover, ILU is difficult to parallelize due to its inherent data dependency. In this paper, we developed a sparse iterative solver with parallelized ILU and triangular solve using block-wise data structure. Compared with the state of art iterative solver on 14 industrial reservoir simulation matrices, the proposed ILU is 5.2x faster (on average) than the state of art iterative solver because of the block-wise data structure, which leads to 2.2x speedup on the total solver runtime. In addition, parallel ILU and triangular solve are developed to further accelerate the solver. To tackle the strong data dependency in ILU and triangular solve, we first partition the algorithm into separated tasks and construct a data flow graph to represent the data dependency. then, tasks are scheduled in parallel according to the topological order of the data flow graph. On an 8-thread multicore architecture, we achieved another 3.6x speedup on ILU factorization, and 3.3x on triangular solve with good scalability.

关键词： Reservoirs Sparse matrices Mathematical model Runtime Multicore processing Jacobian matrices Computational modeling

来源：评论

学校读者我要写书评

暂无评论

On the Limitations of Compilers to Exploit thread-Level parallelism in Embedded Applications

On the Limitations of Compilers to Exploit Thread-Level Para...

引用

international conference on Computer and Information Science (ACIS)

作者： M. Mafijul Islam Department of Computer Science and Engineering Chalmers University of Technology Gothenburg Sweden

With the growing acceptance of multi-core architectures by the industry, devising novel techniques to extract thread-level parallelism from sequential programs has become a fundamental need. the role of compiler along with programming model and architectural innovation is of utmost importance to fully realize the potential performance benefits of the multi-core architectures. this paper evaluates the capabilities and limitations of parallelizing compilers to extract parallelism automatically from the loops present in sequential programs. the applications from embedded benchmark suites EEMBC 1.1 and MiBench are analyzed using the Intel C++ 9.1 Compiler for Linux. the contributions of the paper are manifold: Firstly, the paper shows that on average 10% of the loops can be parallelized automatically by the Intel Compiler. Secondly, we have shown that the auto- parallelizable loops cover only about 12.5% of the total program execution-time. thirdly, we have explored the reasons behind the inability of the compiler to auto-parallelize the majority of the loops. We have found that on average 37.5% and 8% of the loops can't be auto-parallelized because of statically unknown loop trip count and probable data dependence, respectively. Finally, this study identifies the set of loops which comprises the most of the execution time of the programs and shows that compiler, on average, can automatically parallelize about 22% of such loops.

关键词： parallel processing Program processors Hardware Application software Computer science Computer architecture Computer industry Technological innovation Linux Moore's Law

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共287页 << < 276 277 278 279 280 281 282 283 284 285 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：