检索结果-内蒙古大学图书馆

international conference on Computer and Information Technology (CIT)

作者： Wang Lei Zhang Yunquan Zhang Xianyi Liu Fangfang Graduate University of Chinese Academy of Sciences Beijing Lab of Parallel Computing Institute of Software Beijing China State Key Lab of Computing Science Chinese Academy of Sciences Beijing China Lab of Parallel Computing Institute of Software Beijing State Key Lab of Computing Science Chinese Academy of Sciences Beijing

In this paper, the mixed precision algorithm to solve the linear system of equations and the implementation of HPL package are introduced. We use this mixed precision algorithm to improve HPL package on CPU + GPGPU heterogeneous clusters, which is named for GHPL, and give the implementation mechanisms in detail. the experimental results are measured on the platforms of multi-core CPUs and CPU + GPGPU heterogeneous clusters. From the experimental results, we can find out that our GHPL program has good scalability on all the experimental environments and can sustain more than 1.7Teraflops both on the cluster with 16 nodes containing 32 NVIDIA Tesla C1060 GPUs and on the cluster with 8 nodes containing 32 ATI GeForce GTX 295 GPUs, while the average speedup of it with respect to HPL is 3.06 and 2.40 respectively.

关键词： Graphics processing unit Clustering algorithms Convergence Niobium Linear systems Accuracy Benchmark testing

来源：评论

学校读者我要写书评

暂无评论

Neuromorphic processing: a new frontier in scaling computer architecture 14

Neuromorphic processing: a new frontier in scaling computer ...

引用

Proceedings of the 19th international conference on Architectural support for programming languages and operating systems

作者： Jeff Gehlhaar Qualcomm Technologies Inc. San Diego CA USA

ISBN: (纸本)9781450323055

the desire to build a computer that operates in the same manner as our brains is as old as the computer itself. Although computer engineering has made great strides in hardware performance as a result of Dennard scaling, and even great advances in 'brain like' computation, the field still struggles to move beyond sequential, analytical computing architectures. Neuromorphic systems are being developed to transcend the barriers imposed by silicon power consumption, develop new algorithms that help machines achieve cognitive behaviors, and both exploit and enable further research in neuroscience. In this talk I will discuss a system im-plementing spiking neural networks. these systems hold the promise of an architecture that is event based, broad and shallow, and thus more power efficient than conventional computing solu-tions. this new approach to computation based on modeling the brain and its simple but highly connected units presents a host of new challenges. Hardware faces tradeoffs such as density or lower power at the cost of high interconnection overhead. Consequently, software systems must face choices about new language design. Highly distributed hardware systems require complex place and route algorithms to distribute the execution of the neural network across a large number of highly interconnected processing units. Finally, the overall design, simulation and testing process has to be entirely reimagined. We discuss these issues in the context of the Zeroth processor and how this approach compares to other neuromorphic systems that are becoming available.

关键词： spiking neural network parallel computing low power zeroth neural network neuromorphic

来源：评论

学校读者我要写书评

暂无评论

MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications

MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI ...

引用

IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Yasong Cao Mei Wen Junzhong Shen Sheng Liu Zhi Wang Minjin Tang Yahao Fang Jianchao Yang Renyu Yang Yuhan Kang Jiawei Fei College of Computer National University of Defense Technology Changsha China Software Engineering Hunan Normal University Changsha China

the convergence of High-Performance Computing (HPC) and Artificial Intelligence (AI) has become a promising trend. Due to the different computation patterns of HPC and AI applications, it's challenging to design an appropriate architecture to balance their demand. To address this, we propose Matrix Zone (MZ), an enhanced Systolic Array-based matrix engine that accelerates General Matrix Multiplication (GEMM) for both HPC and AI applications. We develop a semi-memory hierarchy to reduce on-chip area consumption and a data stitching method to support multi-precision floating-point processing efficiently. We demonstrate that MZ improves performance for both HPC and AI applications significantly. For AI-GEMM tasks, the performance of MZ is 1.80X (FP32), 15.11X (FPI6), and 3.48X (FPI6-FP32) of the TPU-like model on average, respectively. MZ's performance is more than 10.29X (FP32) and 26.37X (FPI6) of the HPC core in Convolutional (CONV) layers on average, and it is 4.66X (FP32) and 20.75X (FPI6) in Fully Connected (FC) layers on average. For HPC-GEMM tasks, the HPC core + MZ is 6.28X and 1.15X faster than that of the HPC core only and the MZ only on average, respectively. the area of MZ is 2.052 square millimeters.

关键词： Program processors Neural networks parallel processing Systolic arrays System-on-chip Arrays Artificial intelligence

来源：评论

学校读者我要写书评

暂无评论

Hardware Implementation of Blind Source Separation Algorithm Using ZYBO Z7& Xilinx System Generator

Hardware Implementation of Blind Source Separation Algorithm...

引用

international conference on Renewable Energies for Developing Countries (REDEC)

作者： Mohcin Mekhfioui Amal Satif Omar Mouhib Rachid Elgouri Abdelkader Hadjoudja Laamari Hlou Laboratory of Electrical Engineering and Energy Systems Faculty of Science Ibn Tofail University Kenitra Morocco

ISBN: (数字)9781728155951

ISBN: (纸本)9781728155968

Blind Source Separation (BSS) is termed as the extraction of source signals from mixed data without or with little knowledge about the source signals. It is used in many fields of research such as military, medical and industry. Among the many challenges that must be overcome to apply BSS to a real system, implementation restrictions are the most difficult. Software implementations require a significant amount of overhead to make them applicable to real-time systems and have a lower maximum speed of operation than hardware implementations. When speed is desired, the algorithm should be implemented on specialized hardware such as a Field Programmable Gate Array(FPGA) which allows the user to take advantage of parallel computational abilities. this paper describes the methodology for implementing real-time DSP applications on FPGA and the concept of hardware software cosimulation of the Second Order Blind Identification (SOBI) algorithm using MATLAB Simulink and Xilinx System Generator (XSG). Performances of efficient architectures are implemented on FPGA ZYBO Z7 Zynq-7020.

关键词： Field programmable gate arrays Blind source separation Generators Signal processing algorithms Hardware Real-time systems Software packages

来源：评论

学校读者我要写书评

暂无评论

Design of multimedia matching service using manycores and GPGPU

Design of multimedia matching service using manycores and GP...

引用

international conference on Digital Content, Multimedia Technology and its Applications (IDC)

作者： Dong Jin Kim Chulmin Kim Jong Hun Choi Kyu Ho Park Computer Engineering Research Laboratory Electrical Engineering Korea Advanced Institute of Science and Technology Daejeon South Korea

Nowadays, many users are spending their time with enjoying multimedia, and this trend spreads rapidly according to the propagation of smartphones. Multimedia services have tried to attach tag for information of merchandizes related to multimedia, so the multimedia consumers can get detail of those merchandizes, such as price or purchasing information, using attached tag. However, multimedia provider can provide only limited tags while they even cannot support real-time video. In this situation, Multimedia Matching as a Service (MaaS) system is conceptually suggested to let the consumers find items as their preference on real-time video. this system extracts images from video stream, and finds various objects from those images. Since the MaaS system needs a lot of computation power, it should utilize the cloud service which is the recent trend in the computing industry. Due to the circumstance, an efficient internal design for MaaS is required to reduce the cost of using cloud service itself. For the purpose, in this paper, two designs for MaaS system is introduced which are based on manycore system and GPGPU system respectively. One thread per one image method is used for manycore system, and hundreds of cores per one image method is adapted for GPGPU system. Using the intensive experiments, we prove that our design is appropriate for each system. More on that, we compare two designs to obtain the intuition for real system adaption.

关键词： Streaming media Instruction sets Multimedia communication throughput Real time systems parallel processing

来源：评论

学校读者我要写书评

暂无评论

XenSocket: a high-throughput interdomain transport for virtual machines 2007

引用

Proceedings of the 8th ACM/IFIP/USENIX international conference on Middleware

作者： Xiaolan Zhang Suzanne McIntosh Pankaj Rohatgi John Linwood Griffin IBM T.J. Watson Research Center Hawthorne NY

ISBN: (纸本)9783540767770

this paper presents the design and implementation of XenSocket, a UNIX-domain-socket-like construct for high-throughput interdomain (VM-to-VM) communication on the same system. the design of XenSocket replaces the Xen page-flipping mechanism with a static circular memory buffer shared between two domains, wherein information is written by one domain and read asynchronously by the other domain. XenSocket draws on best-practice work in this field and avoids incurring the overhead of multiple hypercalls and memory page table updates by aggregating what were previously multiple operations on multiple network packets into one or more large operations on the shared buffer. While the reference implementation (and name) of XenSocket is written against the Xen virtual machine monitor, the principle behind XenSocket applies broadly across the field of virtual machines.

关键词： stream processing interdomain communication security architectures shared-memory IPC virtual machine Xen

来源：评论

学校读者我要写书评

暂无评论

Microservice-Based Design and Key Technology of the Dispatching and Control Business Middle Platform for the Large Power Grid

Microservice-Based Design and Key Technology of the Dispatch...

引用

IEEE conference on Energy Internet and Energy System Integration (EI2)

作者： Lingtao Zhang Yanyan Liu Wenxi Cui Haitao Dong Shuai Cui Beijing Kedong Electric Power Control System Corporation Limited NARI Group (State Grid Electric Power Research Institute) Corporation Limited Nanjing China

ISBN: (数字)9798331523527

ISBN: (纸本)9798331523534

In order to reduce the service coupling degree of the large power grid dispatching and control system and improve its ability to quickly respond to user needs, a microservice-based large power grid dispatching and control business middle platform has also been proposed and constructed. the microservice-based large power grid model cloud technology, wide-area data distributed streaming processing technology and new human-machine cloud terminal technologies are proposed, and the core business functions such as power grid model service, distributed data processing and human-machine browsing that constitute the business middle platform are developed, And the technical problems such as model on-demand service, high-speed parallel data processing, and local and remote non-differential dispatching are solved, and the business middle platform for the whole network multiplexing of the large power grid control system is constructed, which provides strong support for various applications in the front desk. the application effects of the business middle platform in specific scenarios have been presented, demonstrating the validity of the business middle platform proposed in this paper. the demonstration effect shows that the business middle platform proposed can improve the speed of the front platform of the control system to respond to user needs.

关键词： Cloud computing Human-machine systems Microservice architectures System integration Control systems Data processing Power grids Dispatching Data models Business

来源：评论

学校读者我要写书评

暂无评论

Implementation of A High Speed Layout parallel Prefix Adder for Design Applications

Implementation of A High Speed Layout Parallel Prefix Adder ...

引用

international conference of Electronics, Communication and Aerospace Technology (ICECA)

作者： D. V. N. Bharathi Y. Varthamanan Electronics and Communication Engineering Sathyabama Institute of Science and Technology Chennai Tamil Nadu India

ISBN: (数字)9798350367904

ISBN: (纸本)9798350367911

One of the essential components of applications like signal processing, adders play a crucial role. Integrated circuits are the main technology used in the modern world, and adder modules are required. the arithmetic operationmost often used in digital systems is binary addition. Reliability depends heavily on the efficiency of its *** the digital adder could be made more efficient, it would handle binary operations much better. A microprocessor’s minimum clock cycle time is defined by the speed of its adder. the overall performance of the system is always determined by combining the adders power dissipation, speed, and area. Carry propagation is a performance problem with the addition operation that affects its speed. As a result, VLSI (Very Large-Scale Integration) has been continually focusing on speed increase while reducing covered area. A parallel prefix adder’s speed is the primary consideration when choosing between a ripple carry adder and our preferred alternative. For both latency and coverage area, the best adders in use right now are PPAs, or parallel prefix adders. they are hence the recommended option given the larger number of high-performance adders. An efficient layout parallel prefix adder has been developed and is now accessible to use in design applications. the area (number of LUTs), delay (ns), power, and speed of the suggested designs is better compared to RCA & CLA adders.

关键词： Digital systems Layout Very large scale integration Signal processing Generators Delays Table lookup Power dissipation Integrated circuit reliability Adders

来源：评论

学校读者我要写书评

暂无评论

the infection algorithm: An artificial epidemic approach for dense stereo matching

引用

8th international conference on parallel Problem Solving from Nature, PPSN 2004

作者： Olague, Gustavo de Vega, Francisco Fernández Pérez, Cynthia B. Lutton, Evelyne CICESE Research Center Applied Physics Division Centro de Investigación Científica y de Educación Superior de Ensenada B.C. Km. 107 Carretera Tijuana-Ensenada EnsenadaBC22860 Mexico University of Extremadura Computer Science Department Centro Universitario de Merida C/Sta Teresa de Jornet 38 Mérida06800 Spain INRIA Rocquencourt Domaine de Voluceau BP 105 Le Chesnay Cedex78153 France

ISBN: (纸本)3540230920

We present a new bio-inspired approach applied to a problem of stereo images matching. this approach is based on an artifical epidemic process, that we call "the infection algorithm." the problem at hand is a basic one in computer vision for 3D scene reconstruction. It has many complex aspects and is known as an extremely difficult one. the aim is to match the contents of two images in order to obtain 3D informations which allow the generation of simulated projections from a viewpoint that is different from the ones of the initial photographs. this process is known as view synthesis. the algorithm we propose exploits the image contents in order to only produce the necessary 3D depth information, while saving computational time. It is based on a set of distributed rules, that propagate like an artificial epidemy over the images. Experiments on a pair of real images are presented, and realistic reprojected images have been generated. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Stereo image processing

来源：评论

学校读者我要写书评

暂无评论

Stateful dynamic partial-order reduction

引用

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2006年 4260 LNCS卷 149-167页

作者： Yi, Xiaodong Wang, Ji Yang, Xuejun National Laboratory for Parallel and Distributed Processing Changsha China

ISBN: (纸本)3540474609

State space explosion is the main obstacle for model checking concurrent programs. Among the solutions, partial-order reduction (POR), especially dynamic partial-order reduction (DPOR) [1], is one of the promising approaches. However, DPOR only supports stateless explorations for acyclic state spaces. In this paper, we present the stateful DPOR approach for may-cyclic state spaces, which naturally combines DPOR with stateful model checking to achieve more efficient reduction. Its basic idea is to summarize the interleaving information for all transition sequences starting from each visited state, and infer the necessary partial-order information based on the summarization when a visited state is encountered again. Experiment results on two programs coming from [1] show that both of the costs of space and time could be remarkably reduced by stateful DPOR with rather reasonable extra memory overhead. © Springer-Verlag Berlin Heidelberg 2006.

关键词： Dynamic programming

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：