检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

2,760 篇 会议
56 册 图书
48 篇 期刊文献

馆藏范围

2,862 篇 电子文献
2 种 纸本馆藏

日期分布

学科分类号

2,010 篇 工学
- 1,777 篇 计算机科学与技术...
- 939 篇 软件工程
- 294 篇 信息与通信工程
- 291 篇 电气工程
- 245 篇 电子科学与技术（可...
- 94 篇 控制科学与工程
- 52 篇 机械工程
- 49 篇 生物工程
- 44 篇 光学工程
- 41 篇 生物医学工程（可授...
- 36 篇 仪器科学与技术
- 27 篇 动力工程及工程热...
- 27 篇 化学工程与技术
- 21 篇 土木工程
- 20 篇 力学（可授工学、理...
- 19 篇 材料科学与工程（可...
- 18 篇 建筑学
539 篇 理学
- 385 篇 数学
- 105 篇 物理学
- 55 篇 生物学
- 48 篇 系统科学
- 32 篇 统计学（可授理学、...
- 31 篇 化学
197 篇 管理学
- 121 篇 管理科学与工程(可...
- 81 篇 图书情报与档案管...
- 56 篇 工商管理
50 篇 医学
- 41 篇 临床医学
- 16 篇 基础医学(可授医学...
19 篇 文学
17 篇 经济学
- 17 篇 应用经济学
15 篇 法学
- 14 篇 社会学
11 篇 农学
4 篇 教育学
3 篇 军事学

主题

340 篇 parallel process...
200 篇 parallel process...
190 篇 computer archite...
157 篇 graphics process...
153 篇 parallel archite...
112 篇 parallel algorit...
107 篇 graphics process...
106 篇 hardware
86 篇 image processing
78 篇 computational mo...
73 篇 signal processin...
70 篇 concurrent compu...
66 篇 instruction sets
65 篇 algorithm design...
65 篇 multicore proces...
63 篇 field programmab...
60 篇 parallel program...
59 篇 parallel computi...
53 篇 gpu
48 篇 digital signal p...

机构

10 篇 natl univ def te...
8 篇 college of compu...
6 篇 hosei univ dept ...
6 篇 college of compu...
5 篇 univ aizu dept c...
5 篇 national univers...
5 篇 natl univ def te...
5 篇 city university ...
5 篇 science and tech...
4 篇 chinese acad sci...
4 篇 school of comput...
4 篇 carleton univ sc...
4 篇 univ chinese aca...
4 篇 school of comput...
4 篇 charles univ pra...
4 篇 department of co...
4 篇 school of comput...
4 篇 hainan internati...
4 篇 purple mountain ...
4 篇 department of co...

作者

10 篇 liu jie
9 篇 jack dongarra
8 篇 roman wyrzykowsk...
7 篇 wang qinglin
7 篇 konrad karczewsk...
7 篇 quintana-orti en...
6 篇 gepner pawel
6 篇 peng shietung
6 篇 li kuan-ching
6 篇 li yamin
6 篇 chu wanming
6 篇 prasanna viktor ...
6 篇 rothermel kurt
6 篇 yang chao-tung
5 篇 dongarra jack
5 篇 olas tomasz
5 篇 hannig frank
5 篇 wanlei zhou
5 篇 qian depei
5 篇 ewa deelman

语言

2,839 篇 英文
14 篇 其他
13 篇 中文
1 篇 俄文

检索条件"任意字段=8th International Conference on Algorithms and Architectures for Parallel Processing"

共 2864 条记录，以下是2851-2860 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Hashing Trie: A New Way to Search

Hashing Trie: A New Way to Search

引用

conference on Information and Communication Technology (CICT)

作者： Utkarsh Mishra Achyuth Kasyap P Avinash Chandra Pandey ERP (Digital Applications) HPCL Mumbai Dayanand Sagar Academy of Technology and Management Bangalore Indian Institute of Information Technology Design and Manufacturing Jabalpur

ISBN: (数字)9798331531539

ISBN: (纸本)9798331531546

With the ever-growing quantity of data, there is a need to handle it efficiently. Several approaches have been introduced in the literature to enhance search efficiency. the existing methods use different data structures, such as Hashes and Trees, to reduce the computational complexity. However, Hashes-based methods may perform poorly if a collision occurs, and tree-based methods take longer if the data is present at the last level. therefore, this paper introduces a hybrid method based on the capabilities of hash and trie. the proposed method defines a custom hash function to encode and decode the key string to and from hash numbers for inner hashes. the proposed method creates an inverted index of large text corpora using text-document mapping to improve search efficiency. the performance of the proposed method has been validated in terms of computational time for different input text data split sizes. Besides, the proposed method has also been statistically validated using the Friedman test.

关键词： Hash functions Costs Databases Web pages parallel processing Data structures Information and communication technology Computational complexity Indexing

来源：评论

学校读者我要写书评

暂无评论

Towards Hybrid Computing with Scalable Mass parallelism for High-Performance Cloud Computing of Digital Twins

Towards Hybrid Computing with Scalable Mass Parallelism for ...

引用

Information, Control, and Communication Technologies (ICCT), international conference on

作者： Yury Zatuliveter Elena Fishchenko V.A. Trapeznikov Institute of Control Sciences of the RAS Moscow Russia

ISBN: (数字)9798331517564

ISBN: (纸本)9798331517571

In order to improve the computing performance of the cloud implementations of digital twin models, the possibilities of hybridization of cloud servers using single-chip accelerating general-purpose computers with mass multi-core parallelism are investigated. Such accelerating computers belong to the class of Multi-Processor Systems-on-a-Chip (MPSoC). the variants for system-engineering integration of mass multi-core parallelism of accelerating computer of class MPSoC into a virtual environment of cloud computing resources are considered. On the example of the requirements for the creation of digital twins of nuclear power plants (NPPs), the possibilities of using hybrid computing systems based on the proposed single-chip accelerator with mass multi-core parallelism of the MPSoC class are considered. the proposed multi-SIMD architecture of such accelerators is based on the scalable multiprocessor architecture of accelerating computers PS-2000 for the eponymous hybrid computing complexes, which were produced in a large industrial series in the absence of world analogues. the high efficiency of architecture PS-2000 had been confirmed by the wide practice of application in various fields. At the conceptual level, it is shown that the use of the proposed single-chip accelerating computers with in-chip integration of mass multicore parallelism into the virtual environment of cloud servers opens up opportunities for cloud systems to expand the scaling ranges of computing performance of cloud servers by orders of magnitude. It is necessary when building digital twins of technogenic systems with increased security and computing performance requirements, for example, for NPP.

关键词： Computers Cloud computing Multicore processing Virtual environments Computer architecture parallel processing Hybrid power systems Digital twins Servers Power generation

来源：评论

学校读者我要写书评

暂无评论

Accelerating Biclique Counting on GPU

Accelerating Biclique Counting on GPU

引用

international conference on Data Engineering

作者： Linshan Qiu Zhonggen Li Xiangyu Ke Lu Chen Yunjun Gao Zhejiang University Hangzhou China

ISBN: (数字)9798350317152

ISBN: (纸本)9798350317169

Counting ( $p$ , q)-bicliques in bipartite graphs poses a foundational challenge with broad applications, from densest sub-graph discovery in algorithmic research to personalized content recommendation in practical scenarios. Despite its significance, current leading ( $p$ , q)-biclique counting algorithms fall short, particularly when faced with larger graph sizes and clique scales. Fortunately, the problem's inherent structure, allowing for the independent counting of each biclique starting from every vertex, combined with a substantial set intersections, makes it highly amenable to parallelization. Recent successes in GPU-accelerated algorithms across various domains motivate our exploration into harnessing the parallelism power of GPUs to efficiently address the ( $p$ , q)-biclique counting challenge. We introduce GBC (GPU-based Biclique Counting), a novel approach designed to enable efficient and scalable ( $p$ , q)-biclique counting on GPUs. To address major bottleneck arising from redundant comparisons in set intersections (occupying an average of 90% of the runtime), we introduce a novel data structure that hashes adjacency lists into truncated bitmaps to enable efficient set intersection on GPUs via bit-wise AND operations. Our in-novative hybrid DFS-BFS exploration strategy further enhances thread utilization and effectively manages memory constraints. A composite load balancing strategy, integrating pre-runtime and runtime workload allocation, ensures equitable distribution among threads. Additionally, we employ vertex reordering and graph partitioning strategies for improved compactness and scalability. Experimental evaluations on eight real-life and two synthetic datasets demonstrate that GBC outperforms state-of-the-art algorithms by a substantial margin. In particular, GBC achieves an average speedup of $497.8\times$ , with the largest instance achieving a remarkable $1217.7\times$ speedup when $p=q=8$ .

关键词： Runtime Scalability Instruction sets Memory management Graphics processing units parallel processing Data structures

来源：评论

学校读者我要写书评

暂无评论

Edge optimization detection network for camouflaged targets

Edge optimization detection network for camouflaged targets

引用

Natural Language processing (ICNLP), international conference on

作者： Hao Yuan Haibo Ge Wenhao He Chaofeng Huang School of Electrical Engineering Xi’an University of Posts and Telecommunications Xi’an China

ISBN: (数字)9798350349115

ISBN: (纸本)9798350349122

In order to solve the problem of incomplete spatial information and blurred target boundary in traditional camouflaged target detection (COD), an edge optimization detection network for camouflaged target is proposed. Texture highlight module (thM), Global scale matching module (GSMM), Target boundary exploration module (TBEM) and Boundary inference module (BIM). thM first uses the sensing field to cover the entire multi-stage features extracted by the Res2Net-50 backbone network to realize the global understanding of the visual scene, and then adopts the parallel multi-branch mixed convolution mode to amplify the difference between the target and the background. GSMM encodes the features at the top of the network in channel and spatial dimensions, and can extract the features of different sizes of camouflaged targets from multiple angles. TBEM uses self-attention mechanism to combine lower-level features with higher-level features to deal with the dependency between different boundary pixels in multi-target camouflage. the BIM module uses the boundary guidance factor provided by the TBEM module to guide the inference of the real target and refine the edge details from the features fused by the Attentional Feature Fusion module (AFFM). Quantitative and qualitative experiments were carried out on the public benchmark data set, and the experimental results proved that the proposed algorithm still outperforms the other 8 most advanced models under four objective evaluation indicators.

关键词： Visualization Image edge detection Semantics Object detection Feature extraction Inference algorithms Natural language processing Sensors Reliability Optimization

来源：评论

学校读者我要写书评

暂无评论

Exploiting bit level concurrency in real-time geometric feature extractions

Exploiting bit level concurrency in real-time geometric feat...

引用

Annual international Symposium on Computer Architecture, ISCA

作者： W. Liu T.-F. Yeh W.E. Batchelor R. Cavin Department of Electrical & Computer Engineering North Carolina State University Raleigh NC USA Microelectronics Center of North Carolina USA Semiconductor Research Corporation NC USA

Characteristics and constraints of real-time geometric-feature extraction are discussed. Extracting geometric features from a digital image can be characterized as a computation-intensive task in the environment of a real-time automated vision system. Such tasks require algorithms with a high degree of parallelism and pipelining under the raster-scan I/O constraint. Using the divide-and-conquer technique, many feature extractions have been formulated as a pyramid structure and then mapped into a binary tree. An efficient mapping from a tree structure into a pipelined array of 2logN stages is presented for processing an N*N image. In the proposed mapping structure, the identification of the information growing property allows the exploitation of bit-level concurrency in the architecture design. Accordingly, the design of each staged pipelined processor is simplified containing only bit-serial arithmetic. A single VLSI chip that can generate (p+1)(q+1) moments concurrently in real-time applications is described. this chip has a hardware complexity of O(pq(p+q)log/sup 2/N) units, where p, q stand for the orthogonal orders of the moment. this hardware complexity is better than the O(pq(p+q)/sup 2/log/sup 2/N) units required by the other methods. A single VLSI chip to generate ten moments for a (512*512*8)/pixel image in real time is presented.< >

关键词： Concurrent computing Feature extraction Very large scale integration Hardware Digital images Computer vision Real time systems Machine vision parallel processing Pipeline processing

来源：评论

学校读者我要写书评

暂无评论

A parallel Worklist Algorithm for Modular Analyses

A Parallel Worklist Algorithm for Modular Analyses

引用

IEEE international Workshop on Source Code Analysis and Manipulation

作者： Noah Van Es Quentin Stiévenart Jens Van der Plas Coen De Roover Software Languages Lab Vrije Universiteit Brussel Belgium

ISBN: (数字)9781728192482

ISBN: (纸本)9781728192499

One way to speed up static program analysis is to make use of today's multi-core CPUs by parallelising the analysis. Existing work on parallel analysis usually targets traditional data-How analyses for static, first-order languages such as C. Less attention has been given so far to the parallelisation of more general analyses that can also target dynamic, higherorder languages such as JavaScript. these are significantly more challenging to parallelise, as dependencies between analysis results are only discovered during the analysis itself. State-ofthe-art parallel analyses for such languages are therefore usually limited, both in their applicability and performance gains. In this work, we propose the parallelisation of modular analyses. Modular analyses compute different parts of the analysis in isolation of one another, and therefore offer inherent opportunities for parallelisation that have not been explored so far. In addition, they can be used to develop a general class of analysers for dynamic, higher-order languages. We present a parallel variant of the worklist algorithm that is used to drive such modular analyses. To further speed up its convergence, we show how this algorithm can exploit the monotonicity of the analysis. Existing modular analyses can be parallelised without additional effort by instead employing this parallel worklist algorithm. We demonstrate this for MODF, an inter-procedural modular analysis, and for MODCONC, an inter-process modular analysis. For MODCONC, we reveal an additional opportunity to exploit even more parallelism in the analysis. Our parallel worklist algorithm is implemented and integrated into MAF, a framework for modular program analysis. Using a set of Scheme benchmarks for MODF, we usually observe speedups between 3× and 8× when using 4 workers, and speedups between 8× and 32× when using 16 workers. For MODCONC, we achieve a maximum speedup of 15×.

关键词： Heuristic algorithms conferences Performance gain parallel processing Benchmark testing Convergence

来源：评论

学校读者我要写书评

暂无评论

Moving Average Filter Block Implementation Using USP-Awadhoot Divider

Moving Average Filter Block Implementation Using USP-Awadhoo...

引用

international Baltic Electronics conference, BEC

作者： Udayan S. Patankar Miguel E. Flores Ants Koel Sunil Patankar TJS Department of Electronics TalTech Tallinn University of Technology Tallinn Estonia School of Electronics Don Bosco University Soyapango El Salvador Kavi Kulguru Kalidas Sanskrit University Ramtek India

ISBN: (数字)9798350365115

ISBN: (纸本)9798350365122

In IoT systems, compact, battery-operated circuitry, and rapid data transmission are essential for reducing power consumption and extending battery life. Efficient data transmission requires robust local data processing capabilities supported by appropriate arithmetic and logical units (ALU). Modern processors or field-programmable gate arrays (FPGA) with a suitable ALU are well-suited for meeting these demands. To ensure data quality, effective signal processing before transmission is crucial. A moving average filter (MAF) is an excellent choice for this purpose, providing a balance of speed and precision while utilizing minimal hardware resources, thereby reducing the chip area needed for implementation. this article describes the design and implementation of the moving average low pass filter using the area-efficient novel USP-Awadhoot divider. the proposed USP-Awadhoot divider requires 266 LUTs and 146 FFs for 8-bit implementation using Xilinx FPGA. the proposed moving average filter based on a novel USP-Awadhoot divider is implemented on Nexys A7 XC7A100T-1CSG324C FPGA boards with Xilinx Vivado Design Suite. It is suitable for the cost-effective implementation of IoT and battery-operated applications.

关键词： Program processors Power demand Low-pass filters Signal processing Batteries Table lookup parallel architectures Mobile applications Data communication Field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Leveraging Micro-Services for Ultra-Low Latency: An optimization Model for Service Function Chains Placement

Leveraging Micro-Services for Ultra-Low Latency: An optimiza...

引用

IEEE conference on Network Softwarization (NetSoft)

作者： Hichem Magnouche Guillaume Doyen Caroline Prodhon LIST3N University of Technology of Troyes Troyes France OCIF - IRISA (UMR CNRS 6074) IMT Atlantique Rennes France

ISBN: (数字)9781665406949

ISBN: (纸本)9781665406956

the evolution of the Internet tends toward ever requiring lower latency services. Cloud robotics or drone piloting are service use-cases in which the latency of traffic cannot exceed a few milliseconds. Reducing the latency can be achieved through several means, and micro-services deployed over virtual infrastructures appears as a promising way by enabling service chain reductions, micro-function mutualization and parallelism. However, the placement and routing of such components appears as an harder task to achieve as compared to monolithic approaches of the state of the art. Consequently, we propose in this paper a comprehensive optimization model in charge of placing micro-services in a virtualized network infrastructure, under ultra-low latency constraints while preserving resource consumption. By challenging our model with several realistic scenarios in terms of topology and service function chains (SFC), we demonstrate to what extent it improves the overall performance of SFC by especially minimizing the gap between the expected latency and the actual one, as compared to several competitors, thus making it a well-fitted approach for ultra-low latency services.

关键词： Service function chaining Network topology conferences parallel processing Routing Topology Task analysis

来源：评论

学校读者我要写书评

暂无评论

Integration of text-based applications into service-oriented architectures for transnational digital government 07

Integration of text-based applications into service-oriented...

引用

Proceedings of the 8th annual international conference on Digital government research: bridging disciplines & domains

作者： Andréa Matsunaga Maurício Tsugawa José A. B. Fortes University of Florida Gainesville FL

ISBN: (纸本)9781595935991

Significant efforts are currently being pursued by several countries and IT providers to deploy SOA (Service Oriented Architecture) designs of digital government systems that integrate or implement workflows of multiple software services and data sources. Unfortunately, many existing applications that can be useful in digital government are not implemented as Web Services, a fact that complicates their integration and interoperation within SOAs. To address this problem, this paper presents an approach to easily wrap text-based applications into Web Services. Compared to other application-wrapping approaches, this paper's solution exposes a simpler interface to users, completely hiding the complexities of understanding and developing Web Services. the approach is motivated by, and effective for, the important case of interactive applications, which is harder than batch-oriented applications and has not been considered by other approaches or software development environments. the paper briefly reviews a transnational digital government (TDG) project that requires interoperation and integration of independently developed geographically distributed information processing tools. the characteristics of SOAs are briefly described, along with their suitability for TDG systems and how they can be developed and deployed. the applications underlying the services needed for TDG are introduced and their SOA-relevant characteristics are identified. A framework is described for turning these applications into Web Services that are secure, support interactivity as needed, and do not constrain application functionality. the use of this framework and the evaluation of its benefits are described in the context of the deployment of application services needed by the TDG project.

关键词： transnational information system system integration system interoperability system management

来源：评论

学校读者我要写书评

暂无评论

A Low Complexity Measurement Method for Beam-Forming Network Based on DS-CDMA

A Low Complexity Measurement Method for Beam-Forming Network...

引用

2016 8th IEEE international conference on Communication Software and Networks(ICCSN 2016)

作者： Shi-guang Hao Nan Lu Yun-peng Gao Communication Satellite Department China Academy of Space Technology CAST School of Information Science & Electronics Beijing Institute of Technology BIT

High performance spatial signal processing relies on accurate *** a practical antenna system,due to inevitable aging and heat distortion of the components,there exists an inconsistency between the designed Beam-forming Network(BFN)Weighted Matrix(WM)and the actual value of ***,the complexity of BFN WM measurement is in direct ratio to the channel numbers of *** large-scale phased array antennas,the measurement of the BFN WM requires burdensome *** solve the problem,this paper proposes a novel efficient WM measurement method for BFN based on Direct Sequence-Code Division Multiple Access(DS-CDMA),which significantly reduces the complexity of the test by multi-port testing and parallel signal ***,benefiting from the correlation characteristics of Direct Sequence Spread Spectrum(DSSS)signals,the measurement precision of the proposed method achieves 0.038 in amplitude and 0.511 in *** paper also discusses selections of DSSS *** borrowing the concept of Multi-User Detection(MUD),we proposed a special de-correlation algorithm to solve the problem of using non-orthogonal *** implementation and practical tests have strongly demonstrated the feasibility and accuracy of the proposed method.

关键词： spatial signal processing beam-forming weighted matrix DS-CDMA

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共287页 << < 278 279 280 281 282 283 284 285 286 287 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：