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检索条件"任意字段=8th International Conference on Algorithms and Architectures for Parallel Processing"

共 2864 条记录，以下是71-80 订阅

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Defense Against Textual Backdoors via Elastic Weighted Consolidation-Based Machine Unlearning 24th

Defense Against Textual Backdoors via Elastic Weighted Cons...

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24th international conference on algorithms and architectures for parallel processing, ICA3PP 2024

作者： Xuan, Haojun Wang, Yajie Wu, Huishu Liu, Tao Zhang, Chuan Zhu, Liehuang Beijing Institute of Technology Beijing China China University of Political Science and Law Beijing China China Academy of Information and Communications Technology Beijing China

ISBN: (纸本)9789819615506

Backdoor attacks pose significant threats to Natural Language processing (NLP) models. Various backdoor defense methods for NLP models primarily function by identifying and subsequently manipulating backdoor triggers within provided samples. However, such methods predominantly operate at the level of data filtering, essentially failing to cleanse the affected model. To solve this problem, we present ELUDE—a groundbreaking method designed to excise the backdoor triggers embedded within the corrupted model. ELUDE’s architecture comprises two core components: the backdoor trigger identifier and the backdoor trigger remover, operating synergistically in a pipeline procedure. While the former employs a perplexity-based approach to locate the backdoor trigger, the latter eradicates the inserted backdoor’s influence on the tainted model using machine unlearning. To counteract the issue of catastrophic forgetting engendered by machine unlearning, we incorporate Elastic Weight Consolidation (EWC) within the backdoor trigger remover. Our experiments on SST-2, OLID, and AG News text classification datasets exemplify the efficacy of ELUDE, as comparative results indicate that ELUDE effectively reduces the success rate of three cutting-edge backdoor attack methods by an average of 60%—simultaneously maintaining comparable performance on the original task. © the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Natural language processing systems

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LSSM-SpMM: A Long-Row Splitting and Short-Row Merging Approach for parallel SpMM on PEZY-SC3s 24th

LSSM-SpMM: A Long-Row Splitting and Short-Row Merging Appro...

引用

24th international conference on algorithms and architectures for parallel processing, ICA3PP 2024

作者： Cao, Ligang Wang, Qinglin Yang, Shun Xia, Rui Guo, Weihao Liu, Jie Laboratory of Digitizing Software for Frontier Equipment National University of Defense Technology Changsha410073 China National Key Laboratory of Parallel and Distributed Computing National University of Defense Technology Changsha410073 China

ISBN: (纸本)9789819615506

Sparse Matrix-Dense Matrix Multiplication (SpMM) is a crucial kernel used in a wide range of fields including machine learning and linear algebra solvers. thus, enhancing the performance of SpMM is essential. the uneven distribution of non-zeros in sparse matrices and the tight data dependency between sparse and dense matrices make efficiently running SpMM on various hardware platforms challenging. To address these issues, optimisations are tailored according to the characteristics of the different hardware platforms. In this study, we propose a Long Row Split and Short Row Merge (LSSM) approach on the new MIMD computing platform PEZY-SC3s, utilising the standard Compressed Sparse Row (CSR) format to optimise SpMM. Specifically, LSSM divides the rows of the sparse matrix into short rows (rows with a number of non-zeros less than blockSize) and long rows (rows with a number of non-zeros greater than blockSize), applying splitting to the long rows and merging to the short rows to optimize their computations separately. Additionally, based on the hardware features of PEZY-SC3s, we employed the atomic cache for workload scheduling, SIMD instructions to accelerate computation, and Local Memory to reduce data read-write operations, addressing issues of poor data locality, workload imbalance, and vectorisation during SpMM execution. As the first study of SpMM on PEZY-SC3s, compared with BS-SpMM and RoDe-SpMM implemented on PEZY-SC3s, LSSM-SpMM offers up to 26.17× and 13.59× acceleration on the SuiteSparse and deep learning datasets, respectively, with geometric mean speedups of 1.56× and 1.71×. © the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Deep learning

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parallel Decoding of Trellis Stages for Low Latency Decoding of Tail-Biting Convolutional Codes

Parallel Decoding of Trellis Stages for Low Latency Decoding...

引用

international ITG conference on Source and Channel Coding (SCC)

作者： Amaael Antonini Wenhui Sui Zihan Qu Richard D. Wesel Department of Electrical and Computer Engineering University of California Los Angeles CA USA

ISBN: (数字)9798331522896

ISBN: (纸本)9798331522902

Convolutional codes are widely used in many applications. the encoders can be implemented with a simple circuit. Decoding is often accomplished by the Viterbi algorithm or the maximum a-posteriori decoder of Bahl et al. these algorithms are sequential in nature, requiring a decoding time proportional to the message length. For low latency applications this this latency might be problematic. this paper introduces a low latency decoder for tail-biting convolutional codes TBCCs that processes multiple trellis stages in parallel. the new decoder is designed for hardware with parallel processing capabilities. the overall decoding latency is proportional to the log of the message length. the new decoding architecture is modified into a list decoder, and the list decoding performance can be enhanced by exploiting linearity to expand the search space. Certain modifications to standard TBCCs are supported by the new architecture and improve frame error rate performance.

关键词： Convolutional codes Maximum a posteriori estimation Viterbi algorithm parallel processing Turbo codes Hardware parallel architectures Low latency communication Standards Maximum likelihood decoding

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A Comparative Study of Two Matrix Multiplication algorithms Under Current Hardware architectures 30th

A Comparative Study of Two Matrix Multiplication Algorithms...

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30th international conference on parallel and Distributed processing Techniques, PDPTA 2024, held as part of the World Congress in Computer Science, Computer Engineering and Applied Computing, CSCE 2024

作者： Olatunde, Samuel Colmenares, Eduardo Department of Computer Science McCoy College of Science Mathematics and Engineering Midwestern State University Wichita FallsTX76308 United States

ISBN: (纸本)9783031856372

A widely used computationally intensive scientific kernel, the matrix multiplication algorithm is at the heart of many scientific routines. Resurging fields, such as artificial intelligence (AI), strongly benefit from fast and accurate processing of large matrices. through the years, multiple efforts have been made to derive new algorithms capable of achieving better performance than the naive matrix multiplication approach Θ(n3). One of those is Strassen’s variant Θ(n2.81). this research compares the benefits and differences of using an optimal version of Strassen’s algorithm versus the naive algorithm. the performance analysis makes use of the two most dominant high-performance computing (HPC) architectures available within the Lonestar6 cluster at Texas Advance Computing Center (TACC), the multi-core (CPU) and many-core (GPU) architectures. © the Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： C programming CUDA GPU Matrix Multiplication Strassen’s TACC

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Design and Implementation of FIR Filter Using Different architectures: A Comparative Study

Design and Implementation of FIR Filter Using Different Arch...

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international conference on Signal processing and Communication (ICSC)

作者： Teena Soni Anil Kumar Manoj Kumar Panda PDPM-IIITDM Jabalpur India

ISBN: (数字)9798331511890

ISBN: (纸本)9798331511906

the article proposes a hybrid sparse particle swarm optimization algorithm (HSPSO). this paper also presents an improved low-pass FIR filter design utilizing the HSPSO algorithm. the effectiveness of the proposed algorithm is contrasted with particle swarm optimization and sparse PSO in resolving the FIR filter design problem. HSPSO offered smaller best cost and execution time values. Furthermore, the suggested approach competes with the existing approaches in the literature, providing higher stopband attenuation values and smaller passband ripple values. the proposed work implemented the designed FIR filters, employing various multiplierless techniques, including the canonical signed digit (CSD) number system, fractional CSD (FCSD), distributed arithmetic (DA), and parallel distributed arithmetic (PDA). the comparative study of all the architectures and multiplier-based structure (MULT) is performed for the FPGA and ASIC environments. the DA outperforms all the architecture in area and power. the PDA with decomposition factor 4 provides the highest throughput and also smaller area and power compared with MULT, CSD, and FCSD-based architecture.

关键词： Costs Finite impulse response filters Signal processing algorithms throughput Attenuation Passband Particle swarm optimization Field programmable gate arrays Optimization Arithmetic

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ORL-EPM: A Profit-Aware and Load-Driven Heterogeneous Resource Management Scheme with Collaborative Edge Computing 24th

ORL-EPM: A Profit-Aware and Load-Driven Heterogeneous Resou...

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24th international conference on algorithms and architectures for parallel processing, ICA3PP 2024

作者： Huang, Fengyi Zhang, Yutao Wang, Wenhua Guo, Jianxiong Xu, Yang Fan, Wentao Wang, Tian Hong Kong Baptist University Hong Kong China Hong Kong Baptist University United International College Beijing Normal University Zhuhai China Beijing Normal University Zhuhai China College of Computer Science and Electronic Engineering Hunan University Changsha China

ISBN: (纸本)9789819615414

To address the limitations of energy-efficient but computationally limited ARM64-based AI edge devices and general-purpose edge servers, this paper proposes a Decentralized Collaborative Heterogeneous Edge Computing (DCEC) architecture. this architecture combines edge servers with embedded AI devices to achieve low latency and enhanced computational capabilities. Commercially, the DCEC framework is divided into edge private clouds and edge public clouds, aiming to maximize the profits of Edge Service Providers (ESPs) through dynamic resource management. Considering task dynamism, complexity, and resource heterogeneity, this complex problem is formulated as a multi-stage mixed-integer nonlinear programming (MINLP) problem. We developed the ORL-EPM resource management framework—a three-layer optimization system that adjusts task scheduling based on varying latency sensitivity weights and heterogeneous resource demands. Additionally, we introduced a resource collaboration system based on resource leasing to manage resource overloads and accommodate diverse task complexities. this system includes three Economic Payment Models (EPMs) designed to achieve efficient and profitable resource utilization. Extensive simulation results indicate that this method ensures convergence and closely approximates optimal solutions across various scenarios, significantly outperforming existing methods. Testbed experiments demonstrate that the DCEC architecture can reduce latency by up to 21.83% in real-world applications, notably exceeding previous approaches. © the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Energy efficiency

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Optimized FPGA architectures for High-Speed NTT Computation

Optimized FPGA Architectures for High-Speed NTT Computation

引用

Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT), international conference on

作者： Chetan Harsha Lekkala Sitadevi Bharatula B. Naresh Kumar Reddy K Sarangam Department of ECE Amrita School of Engineering Chennai India

ISBN: (数字)9798350356236

ISBN: (纸本)9798350356243

this research paper aims to enhance the performance of Number theoretic Transform (NTT) operations in cryptographic applications by leveraging the flexibility and parallel processing capabilities of Field Programmable Gate Arrays (FPGAs). NTT, integral to many cryptographic algorithms, often faces real-time performance challenges due to computational demands. By implementing NTT on FPGAs, this approach introduces features such as parallelism, pipelining, and dynamic memory management, significantly improving computational efficiency. the proposed architecture, utilizing 8T SRAM on the AMD Kintex 7 FPGA KC705 Kit, optimizes memory bandwidth and polynomial multiplication, resulting in a robust, high-speed implementation suitable for real-time cryptographic tasks. Simu-lation results demonstrate substantial performance gains, offering a valuable framework for future cryptographic hardware designs.

关键词： Random access memory Transforms Logic gates Hardware Real-time systems Stability analysis Computational efficiency Cryptography Field programmable gate arrays Pipeline processing

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30th international conference on parallel and Distributed processing Techniques, PDPTA 2024, held as part of the World Congress in Computer Science, Computer Engineering and Applied Computing, CSCE 2024

30th International Conference on Parallel and Distributed Pr...

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ISBN: (纸本)9783031856372

the proceedings contain 24 papers. the special focus in this conference is on parallel and Distributed processing Techniques. the topics include: parallel N-Body Performance Comparison: Julia, Rust, and More;REFT: Resource-Efficient Federated Training Framework for Heterogeneous and Resource-Constrained Environments;An Efficient Data Provenance Collection Framework for HPC I/O Workloads;using Minicasts for Efficient Asynchronous Causal Unicast and Byzantine Tolerance;a Comparative Study of Two Matrix Multiplication algorithms Under Current Hardware architectures;Is Manual Code Optimization Still Required to Mitigate GPU thread Divergence? Applying a Flattening Technique to Observe Performance;towards Automatic, Predictable and High-Performance parallel Code Generation;Attack Graph Generation on HPC Clusters;analyzing the Influence of File Formats on I/O Patterns in Deep Learning;inference of Cell–Cell Interactions through Spatial Transcriptomics Data Using Graph Convolutional Neural Networks;natural Product-Like Compound Generation with Chemical Language Models;improved Early–Modern Japanese Printed Character Recognition Rate with Generated Characters;Improved Method for Similar Music Recommendation Using Spotify API;Reconfigurable Virtual Accelerator (ReVA) for Large-Scale Acceleration Circuits;Building Simulation Environment of Reconfigurable Virtual Accelerator (ReVA);vector Register Sharing Mechanism for High Performance Hardware Acceleration;Efficient Compute Resource Sharing of RISC-V Packed-SIMD Using Simultaneous Multi-threading;introducing Competitive Mechanism to Differential Evolution for Numerical Optimization;hyper-heuristic Differential Evolution with Novel Boundary Repair for Numerical Optimization;jump Like a Frog: Optimization of Renewable Energy Prediction in Smart Gird Based on Ultra Long Term Network;vision Transformer-Based Meta Loss Landscape Exploration with Actor-Critic Method;Fast Computation Method for Stopping Condition of Range Restricted

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FPGA-Based 3D EM/MPM Simulation Framework for Medical Image Segmentation Applications

FPGA-Based 3D EM/MPM Simulation Framework for Medical Image ...

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international conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech)

作者： Samit Karmakar Arindam Chakraborty Saptarshi Banerjee Ayantika Mondal Satavisha Dutta Sayak Nandi Electronics & Communication Engineering Dept. Institute of Engineering & Management University of Engineering & Management Kolkata India

ISBN: (数字)9798331520762

ISBN: (纸本)9798331520779

Medical image segmentation is a critical process in identifying disease-infected regions for diagnostic and treatment purposes. this paper introduces an FPGA-based framework for implementing the Expectation Maximization/Markov Random Field (E M/MP M) algorithm in 3D medical image segmentation. FPGA platforms offer unparalleled advantages in terms of parallel processing, speed, and energy efficiency, making them a promising choice for real-time medical image analysis. this proposed framework enables rapid segmentation of 3D images, leveraging the FPGA's on-chip memory and custom logic for efficient pixel classification and data processing. the adaptive design also supports the integration of external RAM for larger datasets. Simulated using Verilog HDL and Quartus Prime, this work demonstrates accurate segmentation results through virtual testing, thus showcasing the system's robustness for medical applications.

关键词： Image segmentation three-dimensional displays Random access memory Medical services parallel processing Real-time systems Energy efficiency Hardware design languages Medical diagnostic imaging Field programmable gate arrays

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Towards Automatic, Predictable and High-Performance parallel Code Generation 30th

Towards Automatic, Predictable and High-Performance Paralle...

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作者： Mullin, Lenore Hains, Gaétan 1400 Washington Ave AlbanyNY12222 United States LACL Université Paris-Est Créteil94000 France

ISBN: (纸本)9783031856372

High-performance architectures have complex features so that reliable production of parallel software is beyond the reach of many Computer Science graduates. Compilers alone cannot guarantee the highest performance and multiple APIs with complex performance features are difficult to master. As a first step towards more comprehensive solutions we are building key elements of a pre-compiler system that will automatically produce predictable, scalable and high-performance code from declarative tensor expressions. In this paper we summarize and analyze a large set of timing experiments of matrix multiplication variants that are mapped to vectorized and multithread code. the analysis covers two high-end target architectures and exhaust a whole space of code, compiler, pragma and parallelism parameters. Our analysis shows how the best choice of parameters is produced from a small set of tests that can converge in a matter of seconds and then predict performance of larger instances to within 25% or much less. Inefficient choices of parameters is also shown to be reliably predicted from small tests, so that our design for a precompiler is guaranteed to be a realistic and portable tool. the generality of our Mathematics of Arrays tensor algebra, and very broad applicability of tensor operations (signal processing, scientific computing, AI, etc.) supports our claim that these experiments and design can be generalized to a general purpose parallel programming tool. © the Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Tensors

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