Diabetic Macular Edema (DME) is a disease of the eye's retina and it's a major factor of causing vision problems and leads towards blindness if it is undiagnosed. Early detection of DME can prevent vision loss...
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ISBN:
(数字)9798331539696
ISBN:
(纸本)9798331539702
Diabetic Macular Edema (DME) is a disease of the eye's retina and it's a major factor of causing vision problems and leads towards blindness if it is undiagnosed. Early detection of DME can prevent vision loss and may reduce diabetic-related problems like cardiovascular issues. therefore, this study presents a method for detecting DME through Optical Coherence Tomography (OCT) and fundus images using transfer learning. the proposed method is based on four stages: Pre-processing, augmentation, segmentation through DeepLabV3+, and binary classification of DME by using two (02) publicly available datasets; the first dataset is Messidor-2, which contains fundus images, and the second dataset is Retinal Images of Optical Coherence Tomography (OCT). In the Messidor-2 dataset, the total number of images is 1744, and Retinal OCT Images dataset consists of 84,495 images total, separated into four categories (CNV, DME, DRUSEN, NORMAL). In the proposed method, Convolutional Neural Networks (CNN) architectures ResNet50 and VGG-19 have been used for the detection of the DME. Convolutional Neural Networks (CNNs) have been extensively used in medical imaging analysis and classification. Using the well-known ResNet50 architecture for classification of each dataset, the proposed model yielded an accuracy of 98.79%, 99% of F1 Score, 98.43% of Precision, and recall of 98.89%. By using VGG-19, the proposed model gives an accuracy of 98.81%, 98.94% of Fl Score, 98.1 % of Precision and recall of 98.73%. When both models (ResNet50 and VGG-19) were compared, the VGG-19 gave the best accuracy.
A semi-dynamic system is presented that is capable of predicting the performance of parallel programs at runtime. the functionality given by the system allows for efficient handling of portability and irregularity of ...
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ISBN:
(纸本)0769525091
A semi-dynamic system is presented that is capable of predicting the performance of parallel programs at runtime. the functionality given by the system allows for efficient handling of portability and irregularity of parallel programs. Two forms of parallelism are addressed: loop level parallelism and task level parallelism.
Dynamic programming techniques are well-established and employed by-various practical algorithms, including the edit-distance algorithm or the dynamic time warping algorithm. these algorithms usually operate in an ite...
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Dynamic programming techniques are well-established and employed by-various practical algorithms, including the edit-distance algorithm or the dynamic time warping algorithm. these algorithms usually operate in an iteration-based manner where new values are computed from values of the previous iteration. the data dependencies enforce synchronization which limits possibilities for internal parallelprocessing. In this paper, we investigate parallel approaches to processing matrix-based dynamic programming algorithms on modern multicore CPUs, Intel Xeon Phi accelerators, and general purpose GPUs. We address boththe problem of computing a single distance on large inputs and the problem of computing a number of distances of smaller inputs simultaneously (e.g., when a similarity query is being resolved). Our proposed solutions yielded significant improvements in performance and achieved speedup of two orders of magnitude when compared to the serial baseline. (C) 2016 Elsevier Ltd. All rights reserved.
A novel extension to external double hashing providing significant reduction to both successful and unsuccessful search lengths is presented. the experimental and analytical results demonstrate the reductions possible...
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ISBN:
(纸本)0769525091
A novel extension to external double hashing providing significant reduction to both successful and unsuccessful search lengths is presented. the experimental and analytical results demonstrate the reductions possible. this method does not restrict the hashing table configuration parameters and utilizes very little additional storage space per bucket. the runtime performance for insertion is slightly greater than for ordinary external double hashing.
Image processing is often considered a good candidate for the application of parallelprocessing because of the large volumes of data and the complex algorithms commonly encountered. this paper presents a tutorial int...
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Image processing is often considered a good candidate for the application of parallelprocessing because of the large volumes of data and the complex algorithms commonly encountered. this paper presents a tutorial introduction to the field of parallel image processing. After introducing the classes of parallelprocessing a brief review of architectures for parallel image processing is presented. Software design for low-level image processing and parallelism in high-level image processing are discussed and an application of parallelprocessing to handwritten postcode recognition is described. the paper concludes with a look at future technology and market trends.
Within the parallel computing domain, field programmable gate arrays (FPGA) are no longer restricted to their traditional role as substitutes for application-specific integrated circuits-as hardware "hidden"...
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ISBN:
(纸本)0769525091
Within the parallel computing domain, field programmable gate arrays (FPGA) are no longer restricted to their traditional role as substitutes for application-specific integrated circuits-as hardware "hidden" from the end user Several high performance computing vendors offer parallel reconfigurable computers employing user-programmable FPGAs. these exciting new architectures allow end-users to, in effect, create reconfigurable coprocessors targeting the computationally intensive parts of each problem. the increased capability of contemporary FPGAs coupled withthe embarrassingly parallel nature of the Jacobi iterative method make the Jacobi method an ideal candidate for hardware acceleration. this paper introduces a parameterized design for a deeply pipelined, highly parallelized IEEE 64-bit floating-point version of the Jacobi method. A Jacobi circuit is implemented using a Xilinx Virtex-II Pro as the target FPGA device. Implementation statistics and performance estimates are presented.
Barrier algorithms are central to the performance of numerous algorithms on scalable, high-performance architectures. Numerous barrier algorithms have been suggested and studied for Non-Uniform Memory Access (NUMA) ar...
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ISBN:
(纸本)0818656026
Barrier algorithms are central to the performance of numerous algorithms on scalable, high-performance architectures. Numerous barrier algorithms have been suggested and studied for Non-Uniform Memory Access (NUMA) architectures, but less work has been done for Cache Only Memory Access (COMA) or attraction memory [1] architectures such as the KSR-1. In this paper, we presented two new barrier algorithmsthat offer the best performance we have recorded on the KSR-1 distributed cache multiprocessor. We discuss the trade-offs and the performance of seven algorithms on two architectures. the new barrier algorithms adapt well to a hierarchical caching memory model and take advantage of parallel communication offered by most multiprocessor interconnection networks,. Performance results are shown for a 256-processor KSR-1 and a 20-processor Sequent Symmetry.
A chip-multiprocessor is one of the promising architecturesthat can overcome the ILP limitation, high power consumption and high heating that current processors face. On a shared memory multiprocessor a performance i...
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ISBN:
(纸本)0769525091
A chip-multiprocessor is one of the promising architecturesthat can overcome the ILP limitation, high power consumption and high heating that current processors face. On a shared memory multiprocessor a performance improvement relies on an efficient communication and synchronization method via shared variables. the TSVM cache combines communication and synchronization withthe coherence maintenance on a chip-multiprocessor that is, the communication and synchronization via shared variables are realized by one coherence transaction through a highspeed on chip inter-connection. the TSVM cache provides several instructions that each instruction has the individual coherence maintenance scheme. the combinations of these instructions can realize the producer-consumers synchronization, mutual exclusion and barrier synchronization with communication easily and systematically. this paper describes how those instructions construct three primitives and shows effect of these primitives using a clock cycle-accurate simulator written in VHDL. the result shows that the TSVM cache can improve a performance of 9.8 times compared with a traditional cache memory, and improve a performance of 2 times compared with a conventional cache memory with synchronization mechanism.
Window-based parallelarchitectures are here considered as target structures for the computation of low and medium level image processingalgorithms. their definition stems from a general reformulation of algorithms, ...
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the appearance of Multicore processors brings high performance computing to the desktop and opens the doors of mainstream computing for parallel computing. this paradigm shift leads the integration of paxallel program...
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ISBN:
(纸本)9783540695004
the appearance of Multicore processors brings high performance computing to the desktop and opens the doors of mainstream computing for parallel computing. this paradigm shift leads the integration of paxallel programming standards for high-end shard-memory machine architectures into desktop programming environments. In this paper we present a performance study of these new systems. We evaluate the performance of an OpenMP shared-memory programming model that is integrated into Microsoft Visual Studio C++ 2005 and Intel C++ compilers on a multicore processor. We benchmarked using the NAS OpenMP high-level applications benchmarks and the EPCC OpenMP low-level benchmarks. We report the basic timings, scalability, and run-time profiles of each benchmark and analyze the running results.
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