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A congestion control algorithm for datacenters

A congestion control algorithm for datacenters

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2013 IEEE 8th international conference on networking, Architecture and Storage, NAS 2013

作者： Zhao, Zhengwei Jiang, Zhixiong Lu, Chunyang Cai, Yushan Bi, Jingping Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China Information Technology Center China National Petroleum Corporation Beijing China

ISBN: (纸本)9780769550343

Recently, there has been renewed interest in latency as a primary metric for mainstream data center applications. In this paper, we propose a coordinated mechanism for congestion control and multi-path transmission to reduce flow completion time in data centers. the approach leverages ECN to adaptively react to congestion, prioritizes flows according to their timeliness requirements, and evenly distributes network traffic across multiple paths. through a real implementation and simulations, we show that our approach can effectively reduce flow completion time under different workflow patterns. Compared to existing solutions based on TCP and flow hashing, our approach achieves an improvement of 30% in application throughput and a reduction of up to 90% in 99th percentile flow completion time for latency-sensitive flows, and a reduction of 50%-80% in average completion time for long background flows. © 2013 IEEE.

关键词： ECN congestion control data center network deadline multipath

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Enabling a Metric Space for Content Search in Information-Centric Networks

Enabling a Metric Space for Content Search in Information-Ce...

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8th international conference on P2P, Parallel, Grid, Cloud and Internet computing (3PGCIC)

作者： Truong, Patrick Peltier, Jean-Francois Orange F-22307 Lannion France

ISBN: (纸本)9780769550947

the emergence of vivacious bandwidth-consuming services leveraged by the overwhelmingly content-centric usage on Internet has fostered over last years a new foundation for networking architecture design. Several Information-Centric networking (ICN) architectures have then been proposed to tackle the challenging problems for content dissemination and distribution. those architectures propose a forwarding plane based on a naming scheme that uniquely identifies content objects in the network regardless of their location. Routing in ICN is thus performed on content names by means of a name resolution service that can be operated independently on the current endpoint-centric networking infrastructure. In order to sketch out the efficient design of such information-centric networks, an important functionality need to be taken into account for resolving information usability which consists in finding appropriate content objects matching users' interest. We propose in this paper a novel forwarding scheme which integrates content search in the network path when resolving content names into locators (where content is actually stored). the content indexing and discovery function relies on distance sensitive hashing based DHT for similarity search between content objects. the proposed routing algorithm can be used for better performance than using classical DHTs for resolving names in ICN. We conceptually embed the high-dimension set of content objects into a low-dimension for reducing processing complexity, which allows us to design an efficient and scalable information-centric forwarding plane with in-network content search.

关键词： Information Centric networking (ICN) in-network content search name resolution distributed Hash Table (DHT) routing indexing distance similarity

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Bit error distribution and mutation patterns of corrupted packets in low-power wireless networks

Bit error distribution and mutation patterns of corrupted pa...

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8th ACM international Workshop on Wireless Network Testbeds, Experimental Evaluation and Characterization, WiNTECH 2013

作者： Schmidt, Florian Ceriotti, Matteo Wehrle, Klaus Communication and Distributed Systems Group RWTH Aachen University Germany

ISBN: (纸本)9781450323642

It is well known that wireless channels produce higher bit error rates than wired connections. However, little knowledge exists about how bit errors are distributed within messages. In this paper, we present results from our experiments in an 802.15.4 sensor node testbed investigating the distribution of errors within erroneous frames. We identify three effects that can only partially be explained by coding and channel conditions: (1) errors are not independently distributed, but to a certain extent bursty, (2) coding leads to some bits being more stable than others, and (3) some content is inherently more stable than other during transmission. We discuss hypotheses on the origins of these effects and give some preliminary ideas on how to leverage them. Copyright 2013 ACM.

关键词： Testbeds

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A HW/SW co-design of execution migration for shared-ISA heterogeneous chip multiprocessors

A HW/SW co-design of execution migration for shared-ISA hete...

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2013 IEEE 8th international conference on networking, Architecture and Storage, NAS 2013

作者： Liu, Hongwei Sang, Bo Huang, Jing Qiu, Ji Gao, Xiang Key Laboratory of Computer System and Architecture Chinese Academy of Sciences No. 6 Kexueyuan South Road Zhongguanchun Haidian District Beijing China Institute of Computing Technology Chinese Academy of Sciences No. 6 Kexueyuan South Road Zhongguanchun Haidian District Beijing China Yuquan Road Shijingshan District Beijing China Loongson Corporation No. 10 Kexueyuan South Road Zhongguanchun Haidian District Beijing China Deptartment of Computer Science Purdue University Lawson Computer Science Build 305 N University Street West Lafayette IN United States

ISBN: (纸本)9780769550343

Heterogeneous multi-core processors have strong potential for performance improvement, energy efficiency and area efficiency, compared to the homogeneous multi-core processors. the present methods of execution migration for heterogeneous multi-core processor suffer in efficiency, cost, compatibility, or programmability. In this paper, we propose a HW/SW code sign migration method based on binary-instrumentation. Our method takes full advantage of the shared-ISA. It enhances the performance of heterogeneous chip multiprocessor with low HW/SW cost. And it's not required to modify source codes or compile system. the experiment results show that the efficiency of our method is 3.29 times of kernel simulation. © 2013 IEEE.

关键词： Energy efficiency

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BFEPM: Best fit energy prediction modeling based on CPU utilization

BFEPM: Best fit energy prediction modeling based on CPU util...

引用

2013 IEEE 8th international conference on networking, Architecture and Storage, NAS 2013

作者： Zhang, Xiao Lu, Jianjun Qin, Xiao School of Computer Science Northwestern Polytechnical University 127 Youyi xi Road Xi'an Shaanxi China Department of Computer Science and Software Engineering Auburn University Auburn AL 36849-5347 United States

ISBN: (纸本)9780769550343

Energy cost becomes a major part of data center operational cost. Computer system consume more power when it runs under high workload. Many past studies focused on how to predict power consumption by performance counters. Some models retrieve performance counters from chips. Some models query performance counters from OS. Most of these researches were verified on several machines and claimed their models were accurate under the test. We found different servers have different energy consumption characters even with same CPU. In this paper, we present BFEPM, a best fit energy prediction model. It choose best model based on the power consumption benchmark result. We illustrate how to use benchmark result to find a best fit model. then we validate the viability and effectiveness of model on all published results. At last, we apply the best fit model on two different machines to estimate the real-time energy consumption. the results show our model can get better results than single model. © 2013 IEEE.

关键词： Green computing

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Parallel algorithm for approximate string matching with K differences

Parallel algorithm for approximate string matching with K di...

引用

2013 IEEE 8th international conference on networking, Architecture and Storage, NAS 2013

作者： Guo, Longjiang Du, Shufang Ren, Meirui Liu, Yu Li, Jinbao He, Jing Tian, Ning Li, Keqin Heilongjiang University School of Computer Science and Technology Harbin 150080 China Key Laboratory of Database and Parallel Computing Heilongjiang China Kennesaw State University Department of Computer Science Kennesaw GA 30144 United States State University of New York Department of Computer Science New Paltz NY 12561 United States

ISBN: (纸本)9780769550343

Approximate string matching using the k-difference technique has been widely applied to many fields such as pattern recognition and computational biology. Data dependency exists in the traditional sequential algorithm. therefore, it is hard to design a parallel algorithm for approximate string matching with k differences. this paper presents a technique to eliminate data dependency. Based on this technique, this paper also presents a parallel algorithm which can calculate the elements in the same row of the edit distance matrix in parallel by eliminating data dependency. the algorithm has high parallelism, but requires synchronization. To validate the proposed algorithm, it is implemented on GPU and multiple-core CPUs. Moreover, the CUDA optimization techniques are also presented in the paper. Finally, experimental results show that, compared with the traditional sequential algorithm on CPU with twenty-four cores, the proposed parallel algorithm achieves speedup of 7-42 on GPU. © 2013 IEEE.

关键词： Graphics processing unit

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Comparisons of memory virtualization solutions for architectures with software-managed TLBs

Comparisons of memory virtualization solutions for architect...

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2013 IEEE 8th international conference on networking, Architecture and Storage, NAS 2013

作者： Tai, Yunfang Cai, Wanwei Liu, Qi Zhang, Ge Wang, Wenzhi State Key Laboratory of Computer Architecture Chinese Academy of Sciences China Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China Loongson Technology Corporation Limited China

ISBN: (纸本)9780769550343

Memory virtualization plays an important role in system virtualization. However, traditional memory virtualization solutions are usually for those architectures with hardware-managed TLBs, such as x86, ARM and so on. the solutions for architectures with software-managed TLBs are rarely mentioned. this paper presents three different memory virtualization solutions for architectures with software-managed TLBs. the difference is that different methods are used to tackle guest TLBs. One is emulating the guest TLBs by software, another is eliminating the guest TLBs and the third is emulating guest TLBs by hardware. After comparisons on hardware platform with MIPS CPUs, it can be seen that the method eliminating guest TLBs can increase the memory bandwidth by more than 100% on average compared to the method emulating guest TLBs by software. After comparisons on simulation platform with MIPS CPUs, it can be seen that the method emulating guest TLBs by hardware would cause about 135% more extra exceptions than the method eliminating guest TLBs. the method eliminating guest TLBs is a good choice when full virtualization is not necessary on the CPUs with software-managed TLBs. © 2013 IEEE.

关键词： Program processors

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IX-level adversaries on entry- and exit-transmission paths in tor network

IX-level adversaries on entry- and exit-transmission paths i...

引用

2013 IEEE 8th international conference on networking, Architecture and Storage, NAS 2013

作者： Liu, Peipeng Shi, Jinqiao Wang, Lihong Wang, Xiao Tan, Qingfeng Institute of Computing Technology Chinese Academy of Sciences 100080 Beijing China Graduate University of Chinese Academy of Sciences Beijing 100039 China Institute of Information Engineering Chinese Academy of Sciences China National Engineering Laboratory for Information Security Technologies IIE China

ISBN: (纸本)9780769550343

Tor is a worldwide publicly deployed low-latency anonymity system. In order to prevent observers from telling where the data came from and where it's going, data packets on the Tor network take a pathway through several intermediate relays. However, nodes selection to build such a pathway is oblivious to Internet routing, so anonymity guarantees can break down in cases where an attacker can correlate traffic across the entry- and exit-segments of a Tor circuit. Although many works have been done to avoid this kind of collusion attack, recent researches [18] indicated that some Internet exchanges (IXes) locating at the entry- and exit-transmission paths in Tor network (that are the paths from the client to the chosen entry node and from the chosen exit node to the destination) are still possible to perform a correlation attack. However, few works have been done to suggest and verify modifications to Tor's path selection algorithm that would help clients avoid an IX-level observer. In this paper, we first, based on the entry-exit pairs chosen by Tor's path selection algorithm, demonstrated that the probability of a single IX observing both ends of an anonymous Tor connection is greater than previously thought. And then, we proposed and evaluated the effectiveness of a simple IX-awareness path selection algorithm that help to resist IX-level attackers. © 2013 IEEE.

关键词： Network security

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Spontaneous reload cache: Mimicking a larger cache with minimal hardware requirement

Spontaneous reload cache: Mimicking a larger cache with mini...

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2013 IEEE 8th international conference on networking, Architecture and Storage, NAS 2013

作者： Zhang, Lunkai Zhang, Mingzhe Fan, Lingjun Wang, Da Ienne, Paolo State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China College of Computer Science Inner Mongolia University China École Polytechnique Fédérale de Lausanne Lausanne Switzerland

ISBN: (纸本)9780769550343

In modern processor systems, on-chip Last Level Caches (LLCs) are used to bridge the speed gap between CPUs and off-chip memory. In recent years, the LRU policy effectiveness in low level caches has been questioned. A significant amount of recent work has explored the design space of replacement policies for CPUs' low level cache systems, and proposed a variety of replacement policies. All these pieces of work are based on the traditional idea of a conventional passive cache, which triggers memory accesses exclusively when there is a cache miss. Such passive cache systems have a theoretical performance upper bound, which is represented by Optimal Algorithm. In this work, we introduce a novel cache system called Spontaneous Reload Cache (SR-Cache). Contrary to passive caches, no matter whether a cache access is a hit or miss, an SR-Cache can actively load or reload an off-chip data block which is predicted to be used in the near future and evict the data block which has the lowest probability to be reused soon. We show that, with minimal hardware overhead, SR-Cache can achieve much better performance than conventional passive caches. © 2013 IEEE.

关键词： Program processors

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the demand for consistent web-based workflow editors 8

The demand for consistent web-based workflow editors

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8th Workshop on Workflows in Support of Large-Scale Science, WORKS 2013

作者： Gesing, Sandra Atkinson, Malcolm Klampanos, Iraklis Galea, Michelle Berthold, Michael R. Barbera, Roberto Scardaci, Diego Terstyanszky, Gabor Kiss, Tamas Kacsuk, Peter University of Notre Dame Ctr for Research Computing University of Edinburgh Informatics Forum 111 Information Technology Center Notre DameIN46556 United States University of Edinburgh Informatics Forum EdinburghEH8 9AB United Kingdom Universität Konstanz FB Informatik and Informationswissenschaft Box 712 Konstanz78457 Germany Italian National Institute of Nuclear Physics Catania95123 Italy University of Westminster 115 New Cavendish Street LondonW1W 6UW United Kingdom Laboratory of Parallel and Distributed Systems MTA SZTAKI Kende Street 13-17 Budapest1111 Hungary

ISBN: (纸本)9781450325028

this paper identifies the high value to researchers in many disciplines of having web-based graphical editors for scientific workflows and draws attention to two technological transitions: good quality editors can now run in a browser and workflow enactment systems are emerging that manage multiple workflow languages and support multi-lingual workflows. We contend that this provides a unique opportunity to introduce multi-lingual graphical workflow editors which in turn would yield substantial benefits: workflow users would find it easier to share and combine methods encoded in multiple workflow languages, the common framework would stimulate conceptual convergence and increased workflow component sharing, and the many workflow communities could share a substantial part of the effort of delivering good quality graphical workflow editors in browsers. the paper examines whether such a common framework is feasible and presents an initial design for a web-based editor, tested with a preliminary prototype. It is not a fait accompli but rather an urgent rallying cry to explore collaboratively a generic web-based framework before investing in many divergent individual implementations.

关键词： Interoperability

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