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检索条件"任意字段=8th International Conference on Parallel Processing and Applied Mathematics"

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8th international conference on Mathematical Software, ICMS 2024

8th International Conference on Mathematical Software, ICMS ...

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8th international conference on Mathematical Software, ICMS 2024

the proceedings contain 37 papers. the special focus in this conference is on Mathematical Software. the topics include: Computing the Determinant of a Dense Matrix over Z;FastECPP over MPI;at...

ISBN: (纸本)9783031645280

the proceedings contain 37 papers. the special focus in this conference is on Mathematical Software. the topics include: Computing the Determinant of a Dense Matrix over Z;FastECPP over MPI;attacking a Levelled Fully Homomorphic Encryption System with Topological Data Analysis;formalising Families of -adic Galois Representations in Lean 4;formalization of the Existence of Frobenius Elements;formalising Analysis in Lean: Compactness and Dimensionality;formalisation of the Category of Hopf Algebras in Lean4;computing the Group of an Algebraic Variety over a Finite Field;computer Classification of Linear Codes Based on Lattice Point Enumeration;software for Proper Vertex-Colouring Exploiting Graph Symmetry;localization in Gromov—Witten theory of Toric Varieties in a Computer Algebra System;massively parallel Methods for Free Resolutions;towards parallel Methods in Birational Geometry;towards parallel Algorithms for Gromov-Witten Invariants of Elliptic Curves;a SageMath Package for Elementary and Sign Vectors with Applications to Chemical Reaction Networks;Symbolic Integration Algorithm Selection with Machine Learning: LSTMs Vs Tree LSTMs;constrained Neural Networks for Interpretable Heuristic Creation to Optimise Computer Algebra Systems;exploring Alternative Machine Learning Models for Variable Ordering in Cylindrical Algebraic Decomposition;machine Learning for Number theory: Unsupervised Learning with L-Functions;approximation of an Inverse of the Incomplete Beta Function;DLMF Standard Reference Tables on Demand;Integrating Mathematical Data and Resources: Advancements in zbMAth Open for Enhanced Mathematical Research Accessibility and Reproducibility;A FAIR File Format for Mathematical Software;predefined Software Environment Runtimes as a Measure for Reproducibility;Towards a FAIR Documentation of Workflows and Models in applied mathematics;monodromy Coordinates;effective Alpha theory Certification Using Interval Arithmetic: Alpha theory over Regions;gröbner Degen

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DLP Based processing-in-Memory Architecture Leveraging Content Addressable Memory 8

DLP Based Processing-in-Memory Architecture Leveraging Conte...

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8th IEEE international conference on Information and Communication Technology, CICT 2024

作者： Vardhan, C Sri Nandan, B.N.H. Kumar, P Tej Krishna, N Teja Peesapati, Rangababu Devarakonda, Vijayakumar Indian Institute of Information Technology Design and Manufacturing Kurnool Department of Electronics and Communication Engineering Kurnool518008 India

ISBN: (纸本)9798331531539

processing-in-Memory (PiM) is one of the rapidly growing paradigms in this world of computer architecture, wherein the data is processed and stored simultaneously within the memory. this architecture will enable us to perform big data computing that require complex data transitions between memory and ALU with reduced latency and improved throughput. this scheme utilizes the concept of Data Level parallelism (DLP), to perform multiple operations with less number of clock cycle using a single instruction. In this paper, ALU operations such as addition, multiplication and logical operations are proposed using PiM with a single instruction by means of fixed memory locations. All the operations are implemented by the concept of Single Instruction Multiple Data (SIMD) techniques. the addition is implemented using the parallel Adder (PA), while multiplication operations are implemented using the karatsuba multiplier. In this work, parallel addition can be implemented with a frequency of 1.42 GHz within the memory, while parallel multiplications can be implemented at a maximum frequency of 2.31 GHz for 2 × 2 bit multiplication by incorporating the karatsuba technique. these implementations consume maximum resources upto 121268 cells of NAND2 × 1 units when inferred in the form of logic cells. Post-layout implementation resulted in an area of area of 83.25 μ m2 for inferring a 1-bit CAM cell. © 2024 IEEE.

关键词： Memory architecture

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Heating Energy Performance Assessment using KNN Classification method: Investigating Test Size, Neighbor Parameter, and Class Count Effects 8

Heating Energy Performance Assessment using KNN Classificati...

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8th IEEE international conference on Image and Signal processing and their Applications, ISPA 2024

作者： Boudjella, Aissa Boudjella, Manal Yasmine Liu, Chuang Samarkand International University of Ttechnology Dept. of Applied Mathematics Samarkand Uzbekistan Bircham International University Dept. Electrical Engineering Miami United States University of Sciences and Technology USTO Dept. of Physics Oran Algeria Samarkand International University of Technology Dept. of Thermal Engineering Samarkand Uzbekistan

ISBN: (纸本)9798350309249

We analyze the energy requirements for assessing the heating load of building systems using the k-Nearest Neighbor (KNN) method for classification. Unsupervised transformations of the dataset are employed in learning algorithms. Two distinct data representation classes are generated separately from the original dataset based on captured heating load magnitudes. the unsupervised transformations of the dataset yield 4 and 8 classes, *** evaluate performance, various test and training sizes are employed, comparing measurement outcomes and predicting class label descriptions for two dataset representations as the parameter for the nearest neighbor (k) ranges from 1 to 20. Results obtained from the simulation indicate that accuracy is influenced by factors such as test size, the k parameter, and dataset class count. the training and test accuracy rates reach maximum values of 95% and 85%, respectively. Keeping k constant, the test size has a negligible impact on accuracy. the classes exhibit three critical regions: 1) Region I, where accuracy fluctuates with increasing k in the interval [1]-[5], and 2) Region II, where accuracy declines with increasing k in the interval [5]-[10]. In Region III k [10]-[20], accuracy remains relatively constant. While reducing the number of classes may result in a slight improvement in accuracy by simplifying the classification task, the trade-offs and complexities of increasing the number of classes for data representation should be carefully considered. Although this approach can lead to a more flexible design, it may slightly reduce accuracy. © 2024 IEEE.

关键词： Learning algorithms

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Using Equivalent Gold Sequences for parallel Data Transmission with Non-orthogonal Code Division 8

Using Equivalent Gold Sequences for Parallel Data Transmissi...

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8th international conference on Information, Control, and Communication Technologies, ICCT 2024

作者： Kukunin, Dmitry Berezkin, Alexander Kirichek, Ruslan Bonch-Bruevich Saint-Petersburg University of Telecommunications Communication Networks and Data Transmission Department Saint-Petersburg Russia Bonch-Bruevich Saint-Petersburg University of Telecommunications Software Engineering and Computer Science Department Saint-Petersburg Russia

ISBN: (纸本)9798331517564

this article describes a new technology for the formation of compacted code structures based on maximum length sequences. the most important distinguishing feature of the code division method presented here is the absence of requirements for the orthogonality of sequences that can be used as address combinations when organizing parallel data transmission. thus, the identification of information recipients is carried out at the physical level using special signal-code structures. At the same time, it is possible to implement a system with anonymous recipients, when any of the recipient nodes does not have information about what data was transferred to other nodes. the communication system model built in accordance with such principles allows the use of the most noise-resistant type of modulation, for example, binary phase-shift keying. this, in turn, ensures the minimum peak factor of the signal. It is also worth noting that the main tool for processing the resulting compacted code structures are dual bases of Galois fields. © 2024 IEEE.

关键词： Code division multiple access

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Proceedings - 2023 8th international conference on Communication, Image and Signal processing, CCISP 2023

Proceedings - 2023 8th International Conference on Communica...

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8th international conference on Communication, Image and Signal processing, CCISP 2023

ISBN: (纸本)9798350305838

the proceedings contain 100 papers. the topics discussed include: FORM: finding the fair-optimal ridesharing matching on road networks;Viterbi soft demodulation algorithm for CPFSK systems;Bangla speech-based emotion detection using a hybrid CNN-transformer approach;synthesizing realistic cracked terrain for virtual arid environment generation;SS-MAF: semi-supervised echocardiographic segmentation using multi-atlas fusion;cardiac medical image segmentation based on parallel fusion network architecture;a target detection method of automotive millimeter wave radar based on deep learning;a modified multivariate variational mode decomposition for multi-channel signal processing;multi-user search on the encrypted network: a lattice-based proxy re-encryption with keyword search;and semantic information consistence network: an improvement method for cardiac medical image segmentation.

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13th international conference on parallel processing and applied mathematics, PPAM 2019

13th International Conference on Parallel Processing and App...

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13th international conference on parallel processing and applied mathematics, PPAM 2019

ISBN: (纸本)9783030432218

the proceedings contain 91 papers. the special focus in this conference is on parallel processing and applied mathematics. the topics include: Performance/Energy Aware Optimization of parallel Applications on GPUs Under Power Capping;improving Energy Consumption in Iterative Problems Using Machine Learning;automatic Software Tuning of parallel Programs for Energy-Aware Executions;overview of Application Instrumentation for Performance Analysis and Tuning;Energy-Efficiency Tuning of a Lattice Boltzmann Simulation Using MERIC;Evaluating the Advantage of Reactive MPI-aware Power Control Policies;application-Aware Power Capping Using Nornir;A New Hardware Counters Based thread Migration Strategy for NUMA Systems;alea – Complex Job Scheduling Simulator;studying the Performance of Vector-Based Quicksort Algorithm;makespan Minimization in Data Gathering Networks with Dataset Release Times;overlapping Schwarz Preconditioner for Fourth Order Multiscale Elliptic Problems;MATLAB Implementation of C1 Finite Elements: Bogner-Fox-Schmit Rectangle;simple Preconditioner for a thin Membrane Diffusion Problem;a Numerical Scheme for Evacuation Dynamics;Additive Average Schwarz with Adaptive Coarse Space for Morley FE;application of Multiscale Computational Techniques to the Study of Magnetic Nanoparticle Systems;clique: A parallel Tool for the Molecular Nanomagnets Simulation and Modelling;Modelling of Limitations of BHJ Architecture in Organic Solar Cells;monte Carlo Study of Spherical and Cylindrical Micelles in Multiblock Copolymer Solutions;parallel Tiled Cache and Energy Efficient Code for Zukers RNA Folding;electronic and Optical Properties of Carbon Nanotubes Directed to their Applications in Solar Cells;the MPFI Library: Towards IEEE 17882015 Compliance;softmax and McFaddens Discrete Choice Under Interval (and Other) Uncertainty;experiments with Heterogenous Automata-Based Multi-agent Systems.

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13th international conference on parallel processing and applied mathematics, PPAM 2019

13th International Conference on Parallel Processing and App...

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13th international conference on parallel processing and applied mathematics, PPAM 2019

ISBN: (纸本)9783030432287

the proceedings contain 91 papers. the special focus in this conference is on parallel processing and applied mathematics. the topics include: A high-performance implementation of a robust preconditioner for heterogeneous problems;hybrid solver for quasi block diagonal linear systems;parallel adaptive cross approximation for the multi-trace formulation of scattering problems;Implementation of parallel 3-D Real FFT with 2-D decomposition on intel xeon phi clusters;Exploiting symmetries of small prime-sized DFTs;parallel computations for various scalarization schemes in multicriteria optimization problems;early performance assessment of the thunderX2 processor for lattice based simulations;An area efficient and reusable HEVC 1D-DCT hardware accelerator;improving locality-aware scheduling with acyclic directed graph partitioning;structure-aware calculation of many-electron wave function overlaps on multicore processors;isoefficiency maps for divisible computations in hierarchical memory systems;OpenMP target device offloading for the SX-Aurora TSUBASA vector engine;On the road to DiPOSH: Adventures in high-performance openSHMEM;click-Fraud detection for online advertising;parallel graph partitioning optimization under PEGASUS DA application global state monitoring;cloud infrastructure automation for scientific workflows;Posit NPB: Assessing the precision improvement in HPC scientific applications;a high-order discontinuous galerkin solver with dynamic adaptive mesh refinement to simulate cloud formation processes;Performance and portability of state-of-art molecular dynamics software on modern GPUs;Exploiting parallelism on shared memory in the QED particle-in-cell code PICADOR with greedy load balancing;lazy stencil integration in multigrid algorithms;parallelized construction of extension velocities for the level-set method;Relative expression classification tree. A preliminary GPU-Based implementation;SIMD-node transformations for non-blocking data structures.

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parallel Combinatory Spread Spectrum System Based on Single Carrier Frequency Domain Equalization in Multipath Fading Channels 8

Parallel Combinatory Spread Spectrum System Based on Single ...

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8th international conference on Communication, Image and Signal processing, CCISP 2023

作者： Yang, Liu Ding, Dan Shen, Zhicheng Hu, Liming Chen, Hao Space Engineering University of PLA Department of Electric and Optical Engineering Beijing China 10th detachment 78156th Unit of PLA Chengdu China Graduate School Space Engineering University of PLA Beijing China

ISBN: (纸本)9798350305838

To solve the problem of performance limitation of direct sequence (DS) spread spectrum system in complex multipath environment, a parallel combinatory spread spectrum (PCSS) framework that combines single carrier frequency domain equalization (SCFDE) is proposed. Higher data rates and large processing gain can be achieved by PCSS transmission and the frequency-selective fading is overcome by frequency domain equalization, which is easy to implement at the receiver for the benefit of fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT). Moreover, in order to balance the transmission rate and reliability in different environments and tasks, an improved PCSS framework with adaptive processing gain is investigated by deploying variable spread spectrum factors under the condition that the number of FFT/IFFT processing points is fixed, by which the control logic is very simple and it is convenient for real implementation. Experimental results demonstrate that the proposed PCSS schemes based on SCFDE show good performance in overcoming multipath fading. In the meanwhile, higher bandwidth utilization can be obtained compared with traditional DS strategy. © 2023 IEEE.

关键词： Multipath fading

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Implementation of A High Speed Layout parallel Prefix Adder for Design Applications 8

Implementation of A High Speed Layout Parallel Prefix Adder ...

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8th international conference on Electronics, Communication and Aerospace Technology, ICECA 2024

作者： Bharathi, D.V.N. Varthamanan, Y. Sathyabama Institute of Science and Technology Electronics and Communication Engineering Tamil Nadu Chennai India

ISBN: (纸本)9798350367904

One of the essential components of applications like signal processing, adders play a crucial role. Integrated circuits are the main technology used in the modern world, and adder modules are required. the arithmetic operationmost often used in digital systems is binary addition. Reliability depends heavily on the efficiency of its *** the digital adder could be made more efficient, it would handle binary operations much better. A microprocessor's minimum clock cycle time is defined by the speed of its adder. the overall performance of the system is always determined by combining the adders power dissipation, speed, and area. Carry propagation is a performance problem with the addition operation that affects its speed. As a result, VLSI (Very Large-Scale Integration) has been continually focusing on speed increase while reducing covered area. A parallel prefix adder's speed is the primary consideration when choosing between a ripple carry adder and our preferred alternative. For both latency and coverage area, the best adders in use right now are PPAs, or parallel prefix adders. they are hence the recommended option given the larger number of high-performance adders. An efficient layout parallel prefix adder has been developed and is now accessible to use in design applications. the area (number of LUTs), delay (ns), power, and speed of the suggested designs is better compared to RCA & CLA adders. © 2024 IEEE.

关键词： Adders

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Multi-vector Monitoring, Detecting and Classifying GPU Side-Channel Attack Vectors on a Secure GPU Execution Framework 8

Multi-vector Monitoring, Detecting and Classifying GPU Side-...

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8th international conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud), I-SMAC 2024

作者： Lungu, Nelson Dash, Bibhuti Bhusan De, Utpal Chandra Dash, Bibek Bikram Singh, Satyendr Patra, Sudhansu Shekhar University of Zambia Electrical and Electronical Engineering Lusaka Zambia Kiit Deemed to be University School of Computer Applications Bhubaneswar India HealthWorksAI Bangalore India Bml Munjal University Computer Science & Engg Department Gurugram India

ISBN: (纸本)9798350376425

Graphics processing Units (GPUs) are increasingly deployed in security-sensitive domains, but their parallel architectures introduce vulnerabilities enabling side-channel attacks to steal sensitive data. Recent works have shown feasible timing, contention, power, and access pattern side-channel attacks against cryptographic implementations, randomness protections, and other workloads on GPUs, highlighting risks of intellectual property theft, cryptographic key extraction, and spying. However, existing academic defences remain inadequate in systematically protecting real-world shader execution. this research aims to design, develop, and evaluate a secure GPU shader execution framework incorporating runtime monitoring, anomaly detection, and response mechanisms for commercial GPUs. the methodology involves implementing and assessing the framework against simulated side-channel attacks on shader benchmarks;this can help secure emerging GPU adoption in sectors like finance, healthcare, and government against rising data breaches. © 2024 IEEE.

关键词： parallel architectures

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