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检索条件"任意字段=8th International Symposium on Parallel Architectures, Algorithms, and Programming, PAAP 2017"

共 26 条记录，以下是11-20 订阅

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A Load Balancing Strategy for Monte Carlo Method in PageRank Problem 8th

A Load Balancing Strategy for Monte Carlo Method in PageRank...

引用

8th international symposium on parallel architectures, algorithms, and programming (paap)

作者： Shao, Bo Lai, Siyan Yang, Bo Xu, Ying Lin, Xiaola Sun Yat Sen Univ Sch Data & Comp Sci Guangzhou Guangdong Peoples R China Sun Yat Sen Univ Minist Educ Key Lab Machine Intelligence & Adv Comp Guangzhou Guangdong Peoples R China

ISBN: (纸本)9789811064425;9789811064418

PageRank algorithm is key component of a wide range of applications. Former study has demonstrated that PageRank problem can be effectively solved through Monte Carlo method. In this paper, we focus on efficiently parallel implementing Monte Carlo method for PageRank algorithm based on GPU. Aiming at GPU, a parallel implementation must consider instruction divergence on the single instruction multiple data (SIMD) compute units. Due to the fact that low-discrepancy sequences are determined sequences, we adopt the low-discrepancy sequences to simulate the random walks in PageRank computations in our load balancing strategy. Furthermore, we allocate each thread of a block to compute a random walk of each vertex with a same low-discrepancy sequence. As a result, no idle thread exists in the PageRank computations and warp execution efficiency is up to 99%. Moreover, our strategy loads the low-discrepancy sequences into shared memory to reduce the data fetch cost. the results of experiments show that our strategy can provide high efficiency for Monte Carlo method in PageRank problem in GPGPU environment.

关键词： Monte Carlo method PageRank GPGPU parallel computing Load balancing

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Speeding Up Convolution on Multi-cluster DSP in Deep Learning Scenarios 8th

Speeding Up Convolution on Multi-cluster DSP in Deep Learnin...

引用

8th international symposium on parallel architectures, algorithms, and programming (paap)

作者： Deng Wenqi Yang Zhenhao Lu Maohui Wang Gai Yang JiangPing Zheng Qilong Univ Sci & Technol China Sch Comp Sci & Technol Hefei Anhui Peoples R China

ISBN: (纸本)9789811064425;9789811064418

Recently, deep learning has achieved great success in artificial intelligent, whose superiority also brought new opportunity for the related research in embedded system. this paper focused on optimizing and speeding the convolution computing, the core operation within convolution neural network based on a multi-cluster digital signal processor, BWDSP. By taking advantage of the BWDSP's architecture and characteristics of convolution computation, a suitable parallel algorithm was designed. Based on features of convolution neural network model structure, an automatic optimization tool for convolution computing with specific arguments was presented as well. the experimental result showed that the parallel algorithm given in this paper is 9.5x faster than GEMM-based algorithm commonly used in GPU and 5.7x faster than the traditional vectorization optimization algorithm. Meanwhile, a comparison was made between the parallel algorithm and tiled-base algorithm widely adopted in system with cache hierarchies, showing that the parallel one could achieve a better performance density of 1.55 times than that of later one, meaning that the work in this paper can make full use of computing resources to make them more efficient.

关键词： Multi-cluster processor Embedded system Deep learning Convolution neural network parallel algorithm

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Architectural Support for Runtime Verification on ccNUMA Multiprocessors

Architectural Support for Runtime Verification on ccNUMA Mul...

引用

8th IEEE international Design and Test symposium (IDT)

作者： Nassar, Ahmed Kurdahi, Fadi J. Univ Calif Irvine Dept EECS Irvine CA 92697 USA

ISBN: (纸本)9781479935253

this paper presents a runtime verification (RV) framework on distributed shared-memory multiprocessors based on explicit functional/concurrency intent specification in the form of temporal logic properties. A generic programming model, that subsumes task and data parallelism, has been wrought along with an automata-based formulation of the RV problem. algorithms are implemented for the construction and minimization of automata checkers that can be executed concurrently with multithreaded applications to assert their correct functioning. the needed architectural supporting mechanisms and the ensuing design tradeoffs are investigated using an approximately-timed transaction-level model. the simulation model confirms scalability of the proposed RV approach to large multiprocessor systems. It also quantifies the increase in the number of processors needed to replenish the monitoring-induced performance degradation.

关键词： parallel architectures temporal logic software debugging automata shared memory systems distributed computing

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Proceedings of the 11th Workshop on parallel programming and Run-Time Management Techniques for Many-Core architectures / 9th Workshop on Design Tools and architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2020

Proceedings of the 11th Workshop on Parallel Programming and...

引用

8th international symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017

ISBN: (纸本)9781450375450

the proceedings contain 5 papers. the topics discussed include: sparse matrix-dense matrix multiplication on heterogeneous CPU+FPGA embedded system;run-time power modeling in embedded GPUs with dynamic voltage and frequency scaling;fault-tolerant online scheduling algorithms for CubeSats;an OpenMP parallel genetic algorithm for design space exploration of heterogeneous multi-processor embedded systems;and automated precision tuning in activity classification systems: a case study.

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OSL: Optimized Bulk Synchronous parallel Skeletons on Distributed Arrays 1

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8th international symposium on Advanced parallel Processing Technologies

作者： Javed, Noman Loulergue, Frederic Univ Orleans LIFO F-45067 Orleans France

ISBN: (数字)9783642036446

ISBN: (纸本)9783642036439

the existing solutions to program parallel architectures range from parallelizing compilers to distributed concurrent programming Intermediate approaches propose a more structured parallelism. Algorithmic skeletons are higher-order functions that capture the patterns of parallel algorithms. the user of the library has just to compose some of the skeletons to write her parallel application. When one is designing a parallel program, the parallel performance is important. It is thus very interesting for the programmer to rely on a simple yet realistic parallel performance model such as the Bulk Synchronous parallel (BSP) model. We present OSL, the Orleans Skeleton Library of BSP algorithmic skeletons in C++. It offers data-parallel skeletons on arrays as well as communication oriented skeletons. the performance of OSL is demonstrated with two applications;heat equation and FFT.

关键词： C++ (programming language)

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On the Performance of parallel Neural Network Implementations on Distributed Memory architectures 08

On the Performance of Parallel Neural Network Implementation...

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8th IEEE international symposium on Cluster Computing and the Grid

作者： Ganeshamoorthy, K. Ranasinghe, D. N. Univ Colombo Sch Comp Dept Computat & Intelligent Syst Colombo 07 Sri Lanka

ISBN: (纸本)9781424442379

In this paper, we study the impact of multi processor memory systems in particular, the distributed memory (I)M) and virtual shared memory (VSM), on the implementation of parallel backpropagation neural network algorithms. In the first instance, neural network is partitioned into sub neural networks by applying a hybrid partitioning scheme. In the second, each partitioned network is evaluated with matrix multiplication. three different sizes of neural networks are used and exchange rate prediction used as a reference problem. parallel implementations for each of the distributed memory and virtual shared memory scenarios is obtained. these algorithms are implemented on a high performance cluster, "Monolith" consisting of over 396 nodes. programming is realized using Message Passing Interface (MPI) library and C-Linda. the partitioned, matrix multiplication has the fastest execution time, and DM/MPI implementation is always faster than the VSM/Linda equivalent. However in VSM/Linda it is possible to allow the parallel neural network to choose the optimum number of processors dynamically.

关键词： VSM DM Hybrid partition parallel neural network

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Automatic generation and assessment of student assignments for parallel programming learning 10th

Automatic generation and assessment of student assignments f...

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10th international symposium on parallel architectures, algorithms and programming, paap 2019

作者： Luo, Zhenxiao Wang, Zelong Wu, Di Hei, Xiaojun Du, Yunfei School of Data and Computer Science Sun Yat-sen University Guangzhou China Guangdong Key Laboratory of Big Data Analysis and Processing Guangzhou510006 China School of Electronic Information and Communications Huazhong University of Science and Technology Wuhan China National Supercomputer Center in Guangzhou Guangzhou China

the course of parallel programming is becoming more and more important for the education of students majoring in computer science. However, it is not easy to learn parallel programming well due to its high theory and practice requirements. In this paper, we design and implement an automatic assignment generation and assessment system to help students learn parallel programming. the assignments can be generated according to user behaviors and thus able to guide students to learn parallel programming step by step. Besides, it can automatically generate an overall assessment of student assignments by using fuzzy string matching, which provides an approximate reference score of objective questions. Subjective questions can be assessed directly by comparing the answer to the reference answer. this system also provides a friendly user interface for students to complete online assignments and let teachers manage their question database. In our teaching practice, students can learn parallel programming more effectively with the help of such an assignment generation and assessment system. © Springer Nature Singapore Pte Ltd. 2020.

关键词： parallel programming

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Enabling software DSM system for grid computing

Enabling software DSM system for grid computing

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8th international symposium on parallel architectures, algorithms and Networks, I-SPAN 2005

作者： Liang, Tyng-Yeu Wu, Chun-Yi Chang, Jyh-Biau Shieh, Ce-Kuen Fan, Pei-Hsin Department of Electrical Engineering National Kaohsiung University of Applied Sciences No.415 Chien-Kung Road Kaohsiung Taiwan Department of Electrical Engineering National Chung Kung University No. 1 Ta-Hsueh Road Tainan Taiwan

ISBN: (纸本)0769525091

In this study, we have successfully developed a grid-enabled software distributed shared memory called Teamster-G. this system provides users with not only a shared memory programming interface but also a transparent resource allocation service to easily develop applications and aggregate distributed resources for solving their problems on the grid environment. Moreover, since the communication cost of maintaining data-consistency is a big problem for the performance of the DSM applications, Teamster-G exploits a cluster cache scheme and a two-level consistency protocol to minimize the number of data-consistency messages transferred over wide area network. We will present the framework and the performance of Teamster-G in this paper. © 2005 IEEE.

关键词： parallel processing systems

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Proceedings - 2017 IEEE international Conference on High Performance Computing and Communications Workshops, HPCCWS 2017 and Multicore and Multithreaded architectures and algorithms, M2A2 2017

Proceedings - 2017 IEEE International Conference on High Per...

引用

2017 IEEE international Conference on High Performance Computing and Communications Workshops, HPCCWS 2017 and 8th Multicore and Multithreaded architectures and algorithms, M2A2 2017

ISBN: (纸本)9781538659304

the proceedings contain 12 papers. the topics discussed include: portable and vendor-independent low-level programming and performance benchmarking for graphics cards and processors;a hybrid parallel genetic algorithm with dynamic migration strategy based on Sunway many-core processor;a framework for WAN optimization and data center selection using NaaS;parallel grouping particle swarm optimization with stream processing paradigm;finding hierarchical network model in insulin production process;efficient generation of parallel spin-images using dynamic loop scheduling;a survey and recommendations for distributed, parallel, single pass, incremental Bayesian classification based on MapReduce for big data;AWEDF: an architecture-aware execution and debugging workflow for a highly reliable chip;performance evaluation of Intel broadwell nodes based supercomputer using computational fluid dynamics and climate applications;an efficient elasticity mechanism for server-based pervasive healthcare applications in cloud environment;and thai sentence generation machine employing fixed patterns.

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parallel Model Checking on Pushdown Systems 16

Parallel Model Checking on Pushdown Systems

引用

16th IEEE ISPA / 17th IEEE IUCC / 8th IEEE BDCloud / 11th IEEE SocialCom / 8th IEEE SustainCom

作者： Wei, Hansheng Chen, Xinyu Ye, Xin Fu, Neng Huang, Yanhong Shi, Jianqi East China Normal Univ Natl Trusted Embedded Software Engn Technol Res C Shanghai Peoples R China Hardware Software Codesign Technol & Applicat Eng Shanghai Peoples R China Shanghai Key Lab Trustworthy Comp Shanghai Peoples R China LIPN Paris France Paris Univ 7 Paris France

ISBN: (纸本)9781728111414

Pushdown systems (PDSs) have been widely used in program verification, such as recursive programs, malware detection, and other model-checking problems. As programs become more complicated, the model-checking process of PDSs represents a real challenge, which is the well-known state explosion problem. this problem may be cost expensive both in terms of memory and time. parallel computing has been introduced to overcome this limitation, especially GPU computing. In this paper, we propose novel parallel algorithms to accelerate model checking on PDSs according to the characteristics of automata-theoretic. To represent the model-checking process on parallel architectures, we propose two new models: multi-threaded P-automaton and multi-threaded Buchi pushdown systems. Moreover, we design a highly efficient data structure for PDSs and dynamic task management to accommodate the GPU. Compared with Moped, a popular model checker for PDSs, our approach achieves promising performance.

关键词： CUDA GPU Model Checking parallel computing Pushdown Systems

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