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检索条件"任意字段=9th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming"

共 385 条记录，以下是151-160 订阅

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Using Data Structure Knowledge for Efficient Lock Generation and Strong Atomicity

Using Data Structure Knowledge for Efficient Lock Generation...

引用

15th acm sigplan symposium on principles and practice of parallel programming

作者： Upadhyaya, Gautam Midkiff, Samuel P. Pai, Vijay S. Purdue Univ W Lafayette IN 47907 USA

ISBN: (纸本)9781605587080

To achieve high-performance on multicore systems, shared-memory parallel languages must efficiently implement atomic operations. the commonly used and studied paradigms for atomicity are fine-grained locking, which is both difficult to program and error-prone;optimistic software transactions, which require substantial overhead to detect and recover from atomicity violations;and compiler-generation of locks from programmer-specified atomic sections, which leads to serialization whenever imprecise pointer analysis suggests the mere possibility of a conflicting operation. this paper presents a new strategy for compiler-generated locking that uses data structure knowledge to facilitate more precise alias and lock generation analyses and reduce unnecessary serialization. Implementing and evaluating these ideas in the Java language shows that the new strategy achieves eight-thread speedups of 0.83 to 5.9 for the five STAMP benchmarks studied, outperforming software transactions on all but one benchmark, and nearly matching programmer-specified fine-grained locks on all but one benchmark. the results also indicate that compiler knowledge of data structures improves the effectiveness of compiler analysis, boosting eight-thread performance by up to 300%. Further, the new analysis allows for software support of strong atomicity with less than 1% overhead for two benchmarks and less than 20% for three others. the strategy also nearly matches the performance of programmer-specified fine-grained locks for the SPECjbb2000 benchmark, which has traditionally not been amenable to static analyses.

关键词： Algorithms Performance Design Automatic lock generation transactional memory parallel programming

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Identifying Scalability Bottlenecks for Large-Scale parallel Programs with Graph Analysis 20

Identifying Scalability Bottlenecks for Large-Scale Parallel...

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25th acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Jin, Yuyang Wang, Haojie Tang, Xiongchao Hoefler, Torsten Liu, Xu Zhai, Jidong Tsinghua Univ Beijing Peoples R China Swiss Fed Inst Technol Zurich Switzerland Coll William & Mary Williamsburg VA 23187 USA

ISBN: (纸本)9781450368186

Scaling a parallel program to modern supercomputers is challenging due to inter-process communication, code serialization, and resource contention. Performance analysis tools for finding such scaling bottlenecks either base on profiling or tracing. Profiling incurs lower overheads but does not capture detailed dependencies needed for root-cause analyses. Tracing collects all information at prohibitive overheads. In this work, we develop ScalAna that uses static analysis techniques to achieve the best of both worlds-it enables the analyzability of traces at a cost similar to profiling. We leverage compiler and runtime lightweight techniques to generate performance graph and perform graph analysis algorithm to detect the root cause of scaling issues. We evaluate ScalAna with real applications on the Tianhe-2 supercomputer. Results show that our approach can effectively locate the root cause of scalability bottlenecks for real applications and incur less than 6.38% overhead (1.89% on average) for up to 2,048 processes.

关键词： Profiling Tools Scaling Loss Analysis Performance Optimization

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CPMA: An Efficient Batch-parallel Compressed Set Without Pointers 24

CPMA: An Efficient Batch-Parallel Compressed Set Without Poi...

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29th acm sigplan Annual symposium on principles and practice of parallel programming (PPoPP)

作者： Wheatman, Brian Burns, Randal Buluc, Aydin Xu, Helen Johns Hopkins Univ Baltimore MD 21218 USA Lawrence Berkeley Natl Lab Lawrence KS USA Georgia Inst Technol Atlanta GA USA

ISBN: (纸本)9798400704352

this paper introduces the batch-parallel Compressed Packed Memory Array (CPMA), a compressed, dynamic, ordered set data structure based on the Packed Memory Array (PMA). Traditionally, batch-parallel sets are built on pointerbased data structures such as trees because pointer-based structures enable fast parallel unions via pointer manipulation. Whencompared with cache-optimized trees, PMAswere slower to update but faster to scan. the batch-parallel CPMA overcomes this tradeoff between updates and scans by optimizing for cache-friendliness. On average, the CPMA achieves 3x faster batch-insert throughput and 4x faster range-query throughput compared with compressed PaC-trees, a state-of-the-art batch-parallel set library based on cache-optimized trees. We further evaluate the CPMA compared with compressed PaC-trees and Aspen, a state-of-the-art system, on a realworld application of dynamic-graph processing. the CPMA is on average 1.2x faster on a suite of graph algorithms and 2x faster on batch inserts when compared with compressed PaC-trees. Furthermore, the CPMA is on average 1.3x faster on graph algorithms and 2x faster on batch inserts compared with Aspen.

关键词： packed memory array batch-parallel compression data structures dynamic graphs

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Scalable GPU Graph Traversal 12

Scalable GPU Graph Traversal

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17th acm sigplan symposium on principles and practice of parallel programming

作者： Merrill, Duane Garland, Michael Grimshaw, Andrew Univ Virginia Charlottesville VA 22903 USA NVIDIA Corp Santa Clara CA USA

ISBN: (纸本)9781450311601

Breadth-first search (BFS) is a core primitive for graph traversal and a basis for many higher-level graph analysis algorithms. It is also representative of a class of parallel computations whose memory accesses and work distribution are both irregular and data-dependent. Recent work has demonstrated the plausibility of GPU sparse graph traversal, but has tended to focus on asymptotically inefficient algorithms that perform poorly on graphs with non-trivial diameter. We present a BFS parallelization focused on fine-grained task management constructed from efficient prefix sum that achieves an asymptotically optimal O(|V|+|E|) work complexity. Our implementation delivers excellent performance on diverse graphs, achieving traversal rates in excess of 3.3 billion and 8.3 billion traversed edges per second using single and quad-GPU configurations, respectively. this level of performance is several times faster than state-of-the-art implementations both CPU and GPU platforms.

关键词： Algorithms performance Breadth-first search GPU graph algorithms parallel algorithms prefix sum graph traversal sparse graph

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parallel execution of multi-set constraint rewrite rules 08

Parallel execution of multi-set constraint rewrite rules

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PPDP 2008: 10th International acm sigplan symposium on principles and practice of Declarative programming

作者： Sulzmann, Martin Lam, Edmund S. L. Programming Logics and Semantics Group IT University of Copenhagen Rued Langgaards Vej 7 2300 Copenhagen S Denmark School of Computing National University of Singapore S16 Level 5 3 Science Drive 2 Singapore 117543 Singapore

ISBN: (纸本)9781605581170

Multi-set constraint rewriting allows for a highly parallel computational model and has been used in a multitude of application domains such as constraint solving, agent specification etc. Rewriting steps can be applied simultaneously as long as they do not interfere with each other. We wish that the underlying constraint rewrite implementation executes rewrite steps in parallel on increasingly popular becoming multi-core architectures. We design and implement efficient algorithms which allow for the parallel execution of multi-set constraint rewrite rules. Our experiments show that we obtain some significant speed-ups on multi-core architectures. Copyright © 2008 acm.

关键词： Computer architecture

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Extending a C-like Language for Portable SIMD programming 12

Extending a C-like Language for Portable SIMD Programming

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17th acm sigplan symposium on principles and practice of parallel programming

作者： Leissa, Roland Hack, Sebastian Wald, Ingo Univ Saarland Compiler Design Lab Saarbrucken Germany Intel Corp Visual Applicat Res Santa Clara CA 95051 USA

ISBN: (纸本)9781450311601

SIMD instructions are common in CPUs for years now. Using these instructions effectively requires not only vectorization of code, but also modifications to the data layout. However, automatic vectorization techniques are often not powerful enough and suffer from restricted scope of applicability;hence, programmers often vectorize their programs manually by using intrinsics: compiler-known functions that directly expand to machine instructions. they significantly decrease programmer productivity by enforcing a very error-prone and hard-to-read assembly-like programming style. Furthermore, intrinsics are not portable because they are tied to a specific instruction set. In this paper, we show how a C-like language can be extended to allow for portable and efficient SIMD programming. Our extension puts the programmer in total control over where and how control-flow vectorization is triggered. We present a type system and a formal semantics of our extension and prove the soundness of the type system. Using our prototype implementation IVL that targets Intel's MIC architecture and SSE instruction set, we show that the generated code is roughly on par with handwritten intrinsic code.

关键词： Languages Performance theory language theory parallel programming polymorphism semantics SIMD SIMT type system vectorization

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High performance synchronization algorithms for multiprogrammed multiprocessors

High performance synchronization algorithms for multiprogram...

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Proceedings of the 5th acm sigplan symposium on principles and practice of parallel programming

作者： Wisniewski, Robert W. Kontothanassis, Leonidas I. Scott, Michael L. Univ of Rochester Rochester United States

Scalable busy-wait synchronization algorithms are essential for achieving good parallel program performance on large scale multiprocessors. Such algorithms include mutual exclusion locks, reader-writer locks, and barrier synchronization. Unfortunately, scalable synchronization algorithms are particularly sensitive to the effects of multiprogramming: their performance degrades sharply when processors are shared among different applications, or even among processes of the same application. In this paper we describe the design and evaluation of scalable scheduler-conscious mutual exclusion locks, reader-writer locks, and barriers, and show that by sharing information across the kernel/application interface we can improve the performance of scheduler-oblivious implementations by more than an order of magnitude.

关键词： parallel algorithms

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PPoPP'11 - Proceedings of the 2011 acm sigplan symposium on principles and practice of parallel programming

PPoPP'11 - Proceedings of the 2011 ACM SIGPLAN Symposium on ...

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16th acm symposium on principles and practice of parallel programming, PPoPP'11

ISBN: (纸本)9781450301190

the proceedings contain 39 papers. the topics discussed include: ordered vs. unordered: a comparison of parallelism and work-efficiency in irregular algorithms;programming the memory hierarchy revisited: supporting irregular parallelism in sequoia;compact data structure and scalable algorithms for the sparse grid technique;a domain-specific approach to heterogeneous parallelism;Copperhead: compiling an embedded data parallel language;OoOJava: software out-of-order execution;SpiceC: scalable parallelism via implicit copying and explicit commit;inferring ownership transfer for efficient message passing;all-window profiling and composable models of cache sharing;ULCC: a user-level facility for optimizing shared cache performance on multicores;ScalaExtrap: trace-based communication extrapolation for SPMD programs;and GRace: a low-overhead mechanism for detecting data races in GPU programs.

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Leapfrogging: A portable technique for implementing efficient futures 93

Leapfrogging: A portable technique for implementing efficien...

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4th acm sigplan symposium on principles and practice of parallel programming, PPOPP 1993

作者： Wagner, David B. Calder, Bradley G. Department of Computer Science University of Colorado Campus Box 430 Boulder80309-0430 United States

ISBN: (纸本)0897915895

A future is a language construct that allows programmers to expose parallelism in applicative languages such as MultiLisp [5] with minimal effort. In this paper we describe a technique for implementing futures, which we call leapfrogging, that reduces blocking due to load imbalance. the utility of leapfrogging is enhanced by the fact that it is completely platform-independent, is free from deadlock, and places a bound on stack sizes that is at most a small constant times the maximum stack size encountered during a sequential execution of the same computation. We demonstrate the performance of leapfrogging using a prototype implementation written in C++.

关键词： C++ (programming language)

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An Adaptive Performance Modeling Tool for GPU Architectures

An Adaptive Performance Modeling Tool for GPU Architectures

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15th acm sigplan symposium on principles and practice of parallel programming

作者： Baghsorkhi, Sara S. Delahaye, Matthieu Patel, Sanjay J. Gropp, William D. Hwu, Wen-mei W. Univ Illinois Urbana IL 61801 USA

ISBN: (纸本)9781605587080

this paper presents an analytical model to predict the performance of general-purpose applications on a GPU architecture. the model is designed to provide performance information to an auto-tuning compiler and assist it in narrowing down the search to the more promising implementations. It can also be incorporated into a tool to help programmers better assess the performance bottlenecks in their code. We analyze each GPU kernel and identify how the kernel exercises major GPU microarchitecture features. To identify the performance bottlenecks accurately, we introduce an abstract interpretation of a GPU kernel, work flow graph, based on which we estimate the execution time of a GPU kernel. We validated our performance model on the NVIDIA GPUs using CUDA (Compute Unified Device Architecture). For this purpose, we used data parallel benchmarks that stress different GPU microarchitecture events such as uncoalesced memory accesses, scratch-pad memory bank conflicts, and control flow divergence, which must be accurately modeled but represent challenges to the analytical performance models. the proposed model captures full system complexity and shows high accuracy in predicting the performance trends of different optimized kernel implementations. We also describe our approach to extracting the performance model automatically from a kernel code.

关键词： Design Measurement Performance Analytical model GPU parallel programming Performance estimation

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