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25th acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Jin, Yuyang Wang, Haojie Tang, Xiongchao Hoefler, Torsten Liu, Xu Zhai, Jidong Tsinghua Univ Beijing Peoples R China Swiss Fed Inst Technol Zurich Switzerland Coll William & Mary Williamsburg VA 23187 USA

ISBN: (纸本)9781450368186

Scaling a parallel program to modern supercomputers is challenging due to inter-process communication, code serialization, and resource contention. Performance analysis tools for finding such scaling bottlenecks either base on profiling or tracing. Profiling incurs lower overheads but does not capture detailed dependencies needed for root-cause analyses. Tracing collects all information at prohibitive overheads. In this work, we develop ScalAna that uses static analysis techniques to achieve the best of both worlds-it enables the analyzability of traces at a cost similar to profiling. We leverage compiler and runtime lightweight techniques to generate performance graph and perform graph analysis algorithm to detect the root cause of scaling issues. We evaluate ScalAna with real applications on the Tianhe-2 supercomputer. Results show that our approach can effectively locate the root cause of scalability bottlenecks for real applications and incur less than 6.38% overhead (1.89% on average) for up to 2,048 processes.

关键词： Profiling Tools Scaling Loss Analysis Performance Optimization

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Deadlock-free buffer configuration for stream computing

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INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2017年第5期31卷 441-450页

作者： Li, Peng Beard, Jonathan C. Buhler, Jeremy D. Washington Univ Dept Comp Sci & Engn St Louis MO 63130 USA

Stream computing is a popular paradigm for parallel and distributed computing, where compute nodes are connected by first-in first-out data channels. Each channel can be considered as a concatenation of several data buffers, including an output buffer for the sender and an input buffer for the receiver. the configuration of buffer sizes impacts the performance as well as the correctness of the application. In this article, we focus on application deadlocks that are caused by incorrect configuration of buffer sizes. We describe three types of deadlock in streaming applications, categorized by how they can be created. To avoid them, we first prove necessary and sufficient conditions for deadlock-free computations;then based on the theorems, we propose both compile-time and runtime solutions for deadlock avoidance.

关键词： Buffer configuration deadlock avoidance feedback channels parallel and distributed computing streaming computing

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Scalable Top-K Retrieval with Sparta 20

Scalable Top-K Retrieval with Sparta

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25th acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Sheffi, Gali Basin, Dmitry Bortnikov, Edward Carmel, David Keidar, Idit Technion Haifa Israel Yahoo Res Haifa Israel Amazon Haifa Israel

ISBN: (纸本)9781450368186

Many big data processing applications rely on a top-k retrieval building block, which selects (or approximates) the k highest-scoring data items based on an aggregation of features. In web search, for instance, a document's score is the sum of its scores for all query terms. Top-k retrieval is often used to sift through massive data and identify a smaller subset of it for further analysis. Because it filters out the bulk of the data, it often constitutes the main performance bottleneck. Beyond the rise in data sizes, today's data processing scenarios also increase the number of features contributing to the overall score. In web search, for example, verbose queries are becoming mainstream, while state-of-the-art algorithms fail to process long queries in real-time. We present Sparta, a practical parallel algorithm that exploits multi-core hardware for fast (approximate) top-k retrieval. thanks to lightweight coordination and judicious context sharing among threads, Sparta scales both in the number of features and in the searched index size. In our web search case study on 50M documents, Sparta processes 12-term queries more than twice as fast as the state-of-the-art. On a tenfold bigger index, Sparta processes queries at the same speed, whereas the average latency of existing algorithms soars to be an order-of-magnitude larger than Sparta's.

关键词： parallel computing multi-threading performance information retrieval web search top-k search

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parallel breadth-first BDD construction

Parallel breadth-first BDD construction

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Proceedings of the 1997 6th acm sigplan symposium on principles and practice of parallel programming

作者： Yang, Bwolen O'Hallaron, David R. Carnegie Mellon Univ Pittsburgh United States

With the increasing complexity of protocol and circuit designs, formal verification has become an important research area and binary decision diagrams (BDDs) have been shown to be a powerful tool in formal verification. this paper presents a parallel algorithm for BDD construction targeted at shared memory multiprocessors and distributed shared memory systems. this algorithm focuses on improving memory access locality through specialized memory managers and partial breadth-first expansion, and on improving processor utilization through dynamic load balancing. the results on a shared memory system show speedups of over two on four processors and speedups of up to four on eight processors. the measured results clearly identify the main source of bottlenecks and point out some interesting directions for further improvements.

关键词： parallel algorithms

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PPoPP'12 - Proceedings of the 2012 acm sigplan symposium on principles and practice of parallel programming

PPoPP'12 - Proceedings of the 2012 ACM SIGPLAN Symposium on ...

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17th acm sigplan symposium on principles and practice of parallel programming, PPoPP'12

ISBN: (纸本)9781450311601

the proceedings contain 57 papers. the topics discussed include: scalable framework for mapping streaming applications onto multi-GPU systems;efficient performance evaluation of memory hierarchy for highly multithreaded graphics processors;extending a C-like language for portable SIMD programming;DOJ: dynamically parallelizing object-oriented programs;GPU-based NFA implementation for memory efficient high speed regular expression matching;concurrent tries with efficient non-blocking snapshots;deterministic parallel random-number generation for dynamic-multithreading platforms;algorithm-based fault tolerance for dense matrix factorizations;revisiting the combining synchronization technique;FlexBFS: a parallelism-aware implementation of breadth-first search on GPU;optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA;and the boat hull model: adapting the roofline model to enable performance prediction for parallel computing.

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An Adaptive Performance Modeling Tool for GPU Architectures

An Adaptive Performance Modeling Tool for GPU Architectures

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15th acm sigplan symposium on principles and practice of parallel programming

作者： Baghsorkhi, Sara S. Delahaye, Matthieu Patel, Sanjay J. Gropp, William D. Hwu, Wen-mei W. Univ Illinois Urbana IL 61801 USA

ISBN: (纸本)9781605587080

this paper presents an analytical model to predict the performance of general-purpose applications on a GPU architecture. the model is designed to provide performance information to an auto-tuning compiler and assist it in narrowing down the search to the more promising implementations. It can also be incorporated into a tool to help programmers better assess the performance bottlenecks in their code. We analyze each GPU kernel and identify how the kernel exercises major GPU microarchitecture features. To identify the performance bottlenecks accurately, we introduce an abstract interpretation of a GPU kernel, work flow graph, based on which we estimate the execution time of a GPU kernel. We validated our performance model on the NVIDIA GPUs using CUDA (Compute Unified Device Architecture). For this purpose, we used data parallel benchmarks that stress different GPU microarchitecture events such as uncoalesced memory accesses, scratch-pad memory bank conflicts, and control flow divergence, which must be accurately modeled but represent challenges to the analytical performance models. the proposed model captures full system complexity and shows high accuracy in predicting the performance trends of different optimized kernel implementations. We also describe our approach to extracting the performance model automatically from a kernel code.

关键词： Design Measurement Performance Analytical model GPU parallel programming Performance estimation

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Distributed data access in AC

Distributed data access in AC

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Proceedings of the 5th acm sigplan symposium on principles and practice of parallel programming

作者： Carlson, William W. Draper, Jesse M. IDA Supercomputing Research Cent Bowie United States

We have modified the C language to support a programming model based on a shared address space with physically distributed memory. With this model users can write programs in which the nodes of a massively parallel processor can access remote memory without message passing. AC provides support for distributed arrays as well as pointers to distributed data. Simple array references and pointer dereferencing are sufficient to generate low-overhead remote reads and writes. We have implemented these ideas in a compiler based on the GNU C compiler and targeted at Cray Research's T3D. Initial performance measurements show that AC generates code for remote accesses which is considerably faster than that of the native compiler for structures up to about 16 words in size and virtually equivalent for larger transfers.

关键词： parallel processing systems

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A collection-oriented programming model for performance portability 2015

A collection-oriented programming model for performance port...

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20th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2015

作者： Muralidharan, Saurav Garland, Michael Catanzaro, Bryan Sidelnik, Albert Hall, Mary University of Utah Salt Lake CityUT United States NVIDIA Corporation Santa ClaraCA United States Baidu Inc. SunnyvaleCA United States

ISBN: (纸本)9781450332057

this paper describes Surge, a collection-oriented programming model that enables programmers to compose parallel computations using nested high-level data collections and operators. Surge exposes a code generation interface, decoupled from the core computation, that enables programmers and autotuners to easily generate multiple implementations of the same computation on various parallel architectures such as multi-core CPUs and GPUs. By decoupling computations from architecture-specific implementation, programmers can target multiple architectures more easily, and generate a search space that facilitates optimization and customization for specific architectures. We express in Surge four real-world benchmarks from domains such as sparse linear-algebra and machine learning and from the same performance-portable specification, generate OpenMP and CUDA C++ implementations. Surge generates efficient, scalable code which achieves up to 1.32x speedup over handcrafted, well-optimized CUDA code.

关键词： parallel architectures

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High performance Fortran for highly irregular problems

High performance Fortran for highly irregular problems

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Proceedings of the 1997 6th acm sigplan symposium on principles and practice of parallel programming

作者： Hu, Y.Charlie Johnsson, S.Lennart Teng, Shang-Hua Harvard Univ Cambridge United States

We present a general data parallel formulation for highly irregular problems in High Performance Fortran (HPF). Our formulation consists of (1) a method for linearizing irregular data structures (2) a data parallel implementation (in HPF) of graph partitioning algorithms applied to the linearized data structure, (3) techniques for expressing irregular communication and nonuniform computations associated with the elements of linearized data structures. We demonstrate and evaluate our formulation on a parallel, hierarchical N-body method for the evaluation of potentials and forces of nonuniform particle distributions. Our experimental results demonstrate that efficient data parallel (HPF) implementations of highly nonuniform problems are feasible with the proper language/compiler/runtime support. Our data parallel N-body code provides a much needed 'benchmark' code for evaluating and improving HPF compilers.

关键词： parallel processing systems

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parallel execution of multi-set constraint rewrite rules 08

Parallel execution of multi-set constraint rewrite rules

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PPDP 2008: 10th International acm sigplan symposium on principles and practice of Declarative programming

作者： Sulzmann, Martin Lam, Edmund S. L. Programming Logics and Semantics Group IT University of Copenhagen Rued Langgaards Vej 7 2300 Copenhagen S Denmark School of Computing National University of Singapore S16 Level 5 3 Science Drive 2 Singapore 117543 Singapore

ISBN: (纸本)9781605581170

Multi-set constraint rewriting allows for a highly parallel computational model and has been used in a multitude of application domains such as constraint solving, agent specification etc. Rewriting steps can be applied simultaneously as long as they do not interfere with each other. We wish that the underlying constraint rewrite implementation executes rewrite steps in parallel on increasingly popular becoming multi-core architectures. We design and implement efficient algorithms which allow for the parallel execution of multi-set constraint rewrite rules. Our experiments show that we obtain some significant speed-ups on multi-core architectures. Copyright © 2008 acm.

关键词： Computer architecture

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