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the STAPL parallel Container Framework 11

The STAPL Parallel Container Framework

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16th acm symposium on principles and practice of parallel programming

作者： Tanase, Gabriel Buss, Antal Fidel, Adam Harshvardhan Papadopoulos, Ioannis Pearce, Olga Smith, Timmie thomas, Nathan Xu, Xiabing Mourad, Nedal Vu, Jeremy Bianco, Mauro Amato, Nancy M. Rauchwerger, Lawrence Texas A&M Univ Parasol Lab Dept Comp Sci & Engn College Stn TX 77843 USA

ISBN: (纸本)9781450301190

the Standard Template Adaptive parallel Library (STAPL) is a parallel programming infrastructure that extends C++ with support for parallelism. It includes a collection of distributed data structures called pContainers that are thread-safe, concurrent objects, i.e., shared objects that provide parallel methods that can be invoked concurrently. In this work, we present the STAPL parallel Container Framework (PCF), that is designed to facilitate the development of generic parallel containers. We introduce a set of concepts and a methodology for assembling a pContainer from existing sequential or parallel containers, without requiring the programmer to deal with concurrency or data distribution issues. the PCF provides a large number of basic parallel data structures (e.g., pArray, pList, pVector, pMatrix, pGraph, pMap, pSet). the PCF provides a class hierarchy and a composition mechanism that allows users to extend and customize the current container base for improved application expressivity and performance. We evaluate STAPL pContainer performance on a CRAY XT4 massively parallel system and show that pContainer methods, generic pAlgorithms, and different applications provide good scalability on more than 16,000 processors.

关键词： parallel programming Languages Libraries Data Structures Languages Design Performance

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Lifeline-based Global Load Balancing 11

Lifeline-based Global Load Balancing

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16th acm symposium on principles and practice of parallel programming

作者： Saraswat, Vijay Kambadur, Prabhanjan Kodali, Sreedhar Grove, David Krishnamoorthy, Sriram Pacific NW Natl Lab Richland WA 99352 USA

ISBN: (纸本)9781450301190

On shared-memory systems, Cilk-style work-stealing [5] has been used to effectively parallelize irregular task-graph based applications such as Unbalanced Tree Search (UTS) [24, 28]. there are two main difficulties in extending this approach to distributed memory. In the shared memory approach, thieves (nodes without work) constantly attempt to asynchronously steal work from randomly chosen victims until they find work. In distributed memory, thieves cannot autonomously steal work from a victim without disrupting its execution. When work is sparse, this results in performance degradation. In essence, a direct extension of traditional work-stealing to distributed memory violates the work-first principle underlying work-stealing. Further, thieves spend useless CPU cycles attacking victims that have no work, resulting in system inefficiencies in multi-programmed contexts. Second, it is non-trivial to detect active distributed termination (detect that programs at all nodes are looking for work, hence there is no work). this problem is well-studied and requires careful design for good performance. Unfortunately, in most existing languages/frameworks, application developers are forced to implement their own distributed termination detection. In this paper, we develop a simple set of ideas that allow work-stealing to be efficiently extended to distributed memory. First, we introduce lifeline graphs: low-degree, low-diameter, fully-connected directed graphs. Such graphs can be constructed from k-dimensional hypercubes. When a node is unable to find work after w unsuccessful steals, it quiesces after informing the outgoing edges in its lifeline graph. Quiescent nodes do not disturb other nodes. A quiesced node is reactivated when work arrives from a lifeline, and itself shares this work with those of its incoming lifelines that are activated. Termination occurs precisely when computation at all nodes has quiesced. In a language such as X10, such passive distributed terminati

关键词： UTS global load balancing distributed computing X10 work-stealing parallel programming Algorithms Design

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ZOOMM: A parallel Web Browser Engine for Multicore Mobile Devices

ZOOMM: A Parallel Web Browser Engine for Multicore Mobile De...

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18th acm sigplan symposium on principles and practice of parallel programming

作者： Cascaval, Calin Fowler, Seth Ortego, Pablo Montesinos Piekarski, Wayne Reshadi, Mehrdad Robatmili, Behnam Weber, Michael Bhavsar, Vrajesh Qualcomm Res Silicon Valley Raleigh NC USA

We explore the challenges in expressing and managing concurrency in browsers on mobile devices. Browsers are complex applications that implement multiple standards, need to support legacy behavior, and are highly dynamic and interactive. We present ZOOMM, a highly concurrent web browser engine prototype and show how concurrency is effectively exploited at different levels: speed up computation performance, preload network resources, and preprocess resources outside the critical path of page loading. On a dual-core Android mobile device we demonstrate that ZOOMM is two times faster than the native WebKit based browser when loading the set of pages defined in the Vellamo benchmark.

关键词： parallel Browser Mobile Multicore

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Merchandiser: Data Placement on Heterogeneous Memory for Task-parallel HPC Applications with Load-Balance Awareness 23

Merchandiser: Data Placement on Heterogeneous Memory for Tas...

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28th acm sigplan Annual symposium on principles and practice of parallel programming, PPoPP 2023

作者： Xie, Zhen Liu, Jie Li, Jiajia Li, Dong University of California Argonne National Laboratory Merced United States University of California Merced United States North Carolina State University United States

ISBN: (纸本)9798400700156

the emergence of heterogeneous memory (HM) provides a cost-effective and high-performance solution to memory-consuming HPC applications. Deciding the placement of data objects on HM is critical for high performance. We reveal a performance problem related to data placement on HM. the problem is manifested as load imbalance among tasks in task-parallel HPC applications. the root of the problem comes from being unaware of parallel-task semantics and an incorrect assumption that bringing frequently accessed pages to fast memory always leads to better performance. To address this problem, we introduce a load balance-aware page management system, named Merchandiser. Merchandiser introduces task semantics during memory profiling, rather than being application-agnostic. Using the limited task semantics, Merchandiser effectively sets up coordination among tasks on the usage of HM to finish all tasks fast instead of only considering any individual task. Merchandiser is highly automated to enable high usability. Evaluating with memory-consuming HPC applications, we show that Merchandiser reduces load imbalance and leads to an average of 17.1% and 15.4% (up to 26.0% and 23.2%) performance improvement, compared with a hardware-based solution and an industry-quality software-based solution. © 2023 acm.

关键词： Semantics

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thread to Strand Binding of parallel Network Applications in Massive Multi-threaded Systems

Thread to Strand Binding of Parallel Network Applications in...

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15th acm sigplan symposium on principles and practice of parallel programming

作者： Radojkovic, Petar Cakarevic, Vladimir Verdu, Javier Pajuelo, Alex Cazorla, Francisco J. Nemirovsky, Mario Valero, Mateo Univ Politecn Cataluna E-08028 Barcelona Spain CSIC Madrid Spain

ISBN: (纸本)9781605587080

In processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a single level of resource sharing, such as pure-SMT or pure-CMP processors. Once the operating system selects the set of applications to simultaneously schedule on the processor (workload), each application/thread must be assigned to one of the hardware contexts (strands). We call this last scheduling step the thread to Strand Binding or TSB. In this paper, we show that the TSB impact on the performance of processors with several levels of shared resources is high. We measure a variation of up to 59% between different TSBs of real multithreaded network applications running on the UltraSPARC T2 processor which has three levels of resource sharing. In our view, this problem is going to be more acute in future multithreaded architectures comprising more cores, more contexts per core, and more levels of resource sharing. We propose a resource-sharing aware TSB algorithm (TSBSched) that significantly facilitates the problem of thread to strand binding for software-pipelined applications, representative of multithreaded network applications. Our systematic approach encapsulates both, the characteristics of multithreaded processors under the study and the structure of the software pipelined applications. Once calibrated for a given processor architecture, our proposal does not require hardware knowledge on the side of the programmer, nor extensive profiling of the application. We validate our algorithm on the UltraSPARC T2 processor running a set of real multithreaded network applications on which we report improvements of up to 46% compared to the current state-of-the-art dynamic schedulers.

关键词： Algorithms Measurement Performance Process Scheduling Simultaneous Multithreading CMT UltraSPARC T2

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Data locality and load balancing in COOL 93

Data locality and load balancing in COOL

引用

4th acm sigplan symposium on principles and practice of parallel programming, PPOPP 1993

作者： Chandra, Rohit Gupta, Anoop Hennessy, John L. Center for Integrated Systems Stanford University StanfordCA94305 United States

ISBN: (纸本)0897915895

Large-scale shared memory multiprocessors typically support a multilevel memory hierarchy consisting of per-processor caches, a local portion of shared memory, and remote shared memory. On such machines, the performance of parallel programs is often limited by the high latency of remote memory references. In this paper we explore how knowledge of the underlying memory hierarchy can be used to schedule computation and distribute data structures, and thereby improve data locality. Our study is done in the context of COOL, a concurrent object-oriented language developed at Stanford. We develop abstractions for the programmer to supply optional information about the data reference patterns of the program. this information is used by the runtime system to distribute tasks and objects so that the tasks execute close (in the memory hierarchy) to the objects they reference. We demonstrate the effectiveness of these techniques by applying them to several applications chosen from the SPLASH parallel benchmark suite. Our experience suggests that improving data locality can be simple through a combination of programmer abstractions and smart runtime scheduling.

关键词： Object oriented programming

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Data structures for task-based priority scheduling 14

Data structures for task-based priority scheduling

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2014 19th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2014

作者： Wimmer, Martin Versaci, Francesco Träff, Jesper Larsson Cederman, Daniel Tsigas, Philippas Faculty of Informatics Parallel Computing Vienna University of Technology 1040 Vienna/Wien Austria Computer Science and Engineering Chalmers University of Technology 412 96 Göteborg Sweden

ISBN: (纸本)9781450326568

We present three lock-free data structures for priority task scheduling: a priority work-stealing one, a centralized one with ρ-relaxed semantics, and a hybrid one combining both concepts. With the single-source shortest path (SSSP) problem as example, we show how the different approaches affect the prioritization and provide upper bounds on the number of examined nodes. We argue that priority task scheduling allows for an intuitive and easy way to parallelize the SSSP problem, notoriously a hard task. Experimental evidence supports the good scalability of the resulting algorithm. the larger aim of this work is to understand the trade-offs between scalability and priority guarantees in task scheduling systems. We show that ρ-relaxation is a valuable technique for improving the first, while still allowing semantic constraints to be satisfied: the lock-free, hybrid κ-priority data structure can scale as well as work-stealing, while still providing strong priority scheduling guarantees, which depend on the parameter κ. Our theoretical results open up possibilities for even more scalable data structures by adopting a weaker form of ρ-relaxation, which still enables the semantic constraints to be respected.

关键词： Scalability

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LogP: Towards a realistic model of parallel computation 93

LogP: Towards a realistic model of parallel computation

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4th acm sigplan symposium on principles and practice of parallel programming, PPOPP 1993

作者： Culler, David Karp, Richard Patterson, David Sahay, Abhijit Erik Schauser, Klaus Santos, Eunice Subramonian, Ramesh Von Eicken, thorsten Computer Science Division University of California Berkeley United States International Computer Science Institute Berkeley United States

ISBN: (纸本)0897915895

A vast body of theoretical research has focused either on overly simplistic models of parallel computation, notably the PRAM, or overly specific models that have few representatives in the real world. Both kinds of models encourage exploitation of formal loopholes, rather than rewarding development of techniques that yield performance across a range of current and future parallel machines. this paper offers a new parallel machine model, called LogP, that reflects the critical technology trends underlying parallel computers. It is intended to serve as a basis for developing fast, portable parallel algorithms and to offer guidelines to machine designers. Such a model must strike a balance between detail and simplicity in order to reveal important bottlenecks without making analysis of interesting problems intractable. the model is based on four parameters that specify abstractly the computing bandwidth, the communication bandwidth, the communication delay, and the efficiency of coupling communication and computation. Portable parallel algorithms typically adapt to the machine configuration, in terms of these parameters. the utility of the model is demonstrated through examples that are implemented on the CM-5. © 1993 acm.

关键词： parallel algorithms

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Multi-Queues Can Be State-of-the-Art Priority Schedulers 22

Multi-Queues Can Be State-of-the-Art Priority Schedulers

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27th acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Postnikova, Anastasiia Koval, Nikita Nadiradze, Giorgi Alistarh, Dan ITMO Univ St Petersburg Russia JetBrains Prague Czech Republic IST Austria Klosterneuburg Austria

ISBN: (纸本)9781450392044

Designing and implementing efficient parallel priority schedulers is an active research area. An intriguing proposed design is the Multi-Queue: given n threads and m >= n distinct priority queues, task insertions are performed uniformly at random, while, to delete, a thread picks two queues uniformly at random, and removes the observed task of higher priority. this approach scales well, and has probabilistic rank guarantees: roughly, the rank of each task removed, relative to remaining tasks in all other queues, is O(m) in expectation. Yet, the performance of this pattern is below that of well-engineered schedulers, which eschew theoretical guarantees for practical efficiency. We investigate whether it is possible to design and implement a Multi-Queue-based task scheduler that is both highly-efficient and has analytical guarantees. We propose a new variant called the Stealing Multi-Queue (SMQ), a cache-efficient variant of the Multi-Queue, which leverages both queue affinity-each thread has a local queue, from which tasks are usually removed;but, with some probability, threads also attempt to steal higher-priority tasks from the other queues-and task batching, that is, the processing of several tasks in a single insert / remove step. these ideas are well-known for task scheduling without priorities;our theoretical contribution is showing that, despite relaxations, this design can still provide rank guarantees, which in turn implies bounds on total work performed. We provide a general SMQ implementation which can surpass state-of-the-art schedulers such as OBIM and PMOD in terms of performance on popular graph-processing benchmarks. Notably, the performance improvement comes mainly from the superior rank guarantees provided by our scheduler, confirming that analytically-reasoned approaches can still provide performance improvements for priority task scheduling. the full version of this paper is available in [24].

关键词： priority scheduling relaxed algorithms concurrency parallel graph processing

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Cache-oblivious wavefront: Improving parallelism of recursive dynamic programming algorithms without losing cache-efficiency 2015

Cache-oblivious wavefront: Improving parallelism of recursiv...

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20th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2015

作者： Tang, Yuan You, Ronghui Kan, Haibin Tithi, Jesmin Jahan Ganapathi, Pramod Chowdhury, Rezaul A. Software School School of Computer Science Fudan University Shanghai Key Laboratory of Intelligent Information Processing Shanghai China Department of Computer Science Stony Brook University Stony BrookNY11790 United States

ISBN: (纸本)9781450332057

State-of-the-art cache-oblivious parallel algorithms for dynamic programming (DP) problems usually guarantee asymptotically optimal cache performance without any tuning of cache parameters, but they often fail to exploit the theoretically best parallelism at the same time. While these algorithms achieve cache-optimality through the use of a recursive divide-and-conquer (DAC) strategy, scheduling tasks at the granularity of task dependency introduces artificial dependencies in addition to those arising from the defining recurrence equations. We removed the artificial dependency by scheduling tasks ready for execution as soon as all its real dependency constraints are satisfied, while preserving the cache-optimality by inheriting the DAC strategy. We applied our approach to a set of widely known dynamic programming problems, such as Floyd-Warshall's All-Pairs Shortest Paths, Stencil, and LCS. theoretical analyses show that our techniques improve the span of 2-way DAC-based Floyd Warshall's algorithm on an n node graph from Θ(nlog2 n) to Θ(n), stencil computations on a d-dimensional hypercubic grid of width w for h time steps from Θ ((d2h) wlog(d+2)-1) to Θ(h), and LCS on two sequences of length n each from Θ (nlog23) to Θ(n). In each case, the total work and cache complexity remain asymptotically optimal. Experimental measurements exhibit a 3-5 times improvement in absolute running time, 10-20 times improvement in burdened span by Cilkview, and approximately the same L1/L2 cache misses by PAPI. Copyright 2015 acm.

关键词： parallel algorithms

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