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User-controllable coherence for high performance shared memory multiprocessors

acm sigplan NOTICES 2003年第10期38卷 73-83页

作者： McCurdy, C Fischer, C Univ Wisconsin Dept Comp Sci Madison WI 53706 USA

In programming high performance applications, shared address-space platforms are preferable for fine-grained computation, while distributed address-space platforms are more suitable for coarse-grained computation. However, currently only distributed address-space systems scale beyond the low hundreds of processors. In this paper we introduce a hybrid architecture that allows users to trade off local memory usage for coherence communication, making possible larger-scale shared memory architectures. We introduce a programming model and examine possible implementations of hardware mechanisms, evaluating some of the trade-offs inherent in each. Preliminary experiments on an application with particularly fine-grained communication requirements indicate that effective placement of directives can reduce coherence communication by more than a factor of 10 for 64 processors.

关键词： performance design languages parallel computation shared memory architectures distributed memory architectures irregular computation

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Towards execution time estimation in abstract machine-based languages 08

Towards execution time estimation in abstract machine-based ...

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PPDP 2008: 10th International acm sigplan symposium on principles and practice of Declarative programming

作者： Mera, E. Lopez, P. Carro, M. Hermenegildo, M. Complutense University of Madrid IMDEA Software Technical U. of Madrid U. of New Mexico

ISBN: (纸本)9781605581170

Abstract machines provide a certain separation between platform-dependent and platform-independent concerns in compilation. Many of the differences between architectures are encapsulated in the specific abstract machine implementation and the bytecode is left largely architecture independent. Taking advantage of this fact, we present a framework for estimating upper and lower bounds on the execution times of logic programs running on a bytecode-based abstract machine. Our approach includes a one-time, program-independent profiling stage which calculates constants or functions bounding the execution time of each abstract machine instruction. then, a compile-time cost estimation phase, using the instruction timing information, infers expressions giving platform-dependent upper and lower bounds on actual execution time as functions of input data sizes for each program. Working at the abstract machine level makes it possible to take into account low-level issues in new architectures and platforms by just reexecuting the calibration stage instead of having to tailor the analysis for each architecture and platform. Applications of such predicted execution times include debugging/verification of time properties, certification of time properties in mobile code, granularity control in parallel/distributed computing, and resource-oriented specialization. Copyright © 2008 acm.

关键词： Logic programming

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Using thread-level speculation to simplify manual parallelization

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acm sigplan NOTICES 2003年第10期38卷 1-12页

作者： Prabhu, MK Olukotun, K Stanford Univ Comp Syst Lab Stanford CA 94305 USA

In this paper, we provide examples of how thread-level speculation (TLS) simplifies manual parallelization and enhances its performance. A number of techniques for manual parallelization using TLS are presented and results are provided that indicate the performance contribution of each technique on seven SPEX CPU2000 benchmark applications. We also provide indications of the programming effort required to parallelize each benchmark. TLS parallelization yielded a 110% speedup on our four floating point applications and a 70% speedup on our three integer applications, while requiring only approximately 80 programmer hours and 150 lines of non-template code per application. these results support the idea that manual parallelization using TLS is an efficient way to extract fine-grain thread-level parallelism.

关键词： design algorithms performance measurement chip multiprocessor data speculation manual parallel programming multithreading feedback-driven optimization

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A hierarchical approach to reducing communication in parallel graph algorithms 2015

A hierarchical approach to reducing communication in paralle...

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20th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2015

作者： Harshvardhan Amato, Nancy M. Rauchwerger, Lawrence Parasol Laboratory Department of Computer Science and Engineering Texas A and M University United States

ISBN: (纸本)9781450332057

Large-scale graph computing has become critical due to the ever-increasing size of data. However, distributed graph computations are limited in their scalability and performance due to the heavy communication inherent in such computations. this is exacerbated in scale-free networks, such as social and web graphs, which contain hub vertices that have large degrees and therefore send a large number of messages over the network. Furthermore, many graph algorithms and computations send the same data to each of the neighbors of a vertex. Our proposed approach recognizes this, and reduces communication performed by the algorithm without change to user-code, through a hierarchical machine model imposed upon the input graph. the hierarchical model takes advantage of locale information of the neighboring vertices to reduce communication, both in message volume and total number of bytes sent. It is also able to better exploit the machine hierarchy to further reduce the communication costs, by aggregating traffic between different levels of the machine hierarchy. Results of an implementation in the STAPL GL shows improved scalability and performance over the traditional level-synchronous approach, with 2.5 × - 8× improvement for a variety of graph algorithms at 12, 000+ cores.

关键词： Big data

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Reference idempotency analysis: A framework for optimizing speculative execution

Reference idempotency analysis: A framework for optimizing s...

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8th acm sigplan symposium on principles and practice of parallel programming

作者： Seon Wook Kim Ooi, C.-L. Eigenmann, R. Falsafi, B. Vijaykumar, T.N. Intel Corp. Champaign IL United States

Recent proposals for multithreaded architectures allow threads with unknown dependences to execute speculatively in parallel. these architectures use hardware speculative storage to buffer uncertain data, track data dependences and roll back incorrect executions. Because all memory references access the speculative storage, current proposals implement this storage using small memory structures for fast access. the limited capacity of the speculative storage causes considerable performance loss due to speculative storage overflow whenever a thread's speculative state exceeds the storage capacity. Larger threads exacerbate the over-flow problem but are preferable to smaller threads, as larger threads uncover more parallelism. In this paper, we discover a new program property called memory reference idempotency. Idempotent references need not be tracked in the speculative storage, and instead can directly access non-speculative storage (i.e., the conventional memory hierarchy). thus, we reduce the demand fo r speculative storage space. We define a formal framework for reference idempotency and present a novel compiler-assisted speculative execution model. We prove the necessary and sufficient conditions for reference idempotency using our model. We present a compiler algorithm to label idempotent memory references for the hardware. Experimental results show that for our benchmarks, over 60% of the references in non-parallelizable program sections are idempotent.

关键词： parallel processing systems

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parallel binary code analysis 21

Parallel binary code analysis

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26th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2021

作者： Meng, Xiaozhu Anderson, Jonathon M. Mellor-Crummey, John Krentel, Mark W. Miller, Barton P. Milaković, Sran Department of Computer Science Rice University Houston TX United States Computer Sciences Department University of Wisconsin-Madison MadisonWI United States

Binary code analysis is widely used to help assess a program9;s correctness, performance, and provenance. Binary analysis applications often construct control flow graphs, analyze data flow, and use debugging infor... 详细信息

ISBN: (纸本)9781450382946

Binary code analysis is widely used to help assess a program's correctness, performance, and provenance. Binary analysis applications often construct control flow graphs, analyze data flow, and use debugging information to understand how machine code relates to source lines, inlined functions, and data types. To date, binary analysis has been single-threaded, which is too slow for convenient use in performance tuning workflows where it is used to help attribute performance to complex applications with large binaries. this paper describes our design and implementation for accelerating the task of constructing control flow graphs (CFGs) from binaries by using multithreading. Prior research focuses on algorithms for analysis of challenging code constructs encountered while constructing CFGs, including functions sharing code, jump tables, non-returning functions, and tail calls. these algorithms are described from a program analysis perspective and are not suitable for direct parallel implementation. We abstract the task of constructing CFGs as repeated applications of several core CFG operations that include creating functions, basic blocks, and edges. We then derive CFG operation dependency, commutativity, and monotonicity. these operation properties guide our design of a new parallel analysis for constructing CFGs. Using 64 threads, we achieved as much as 25× speedup for constructing CFGs and 8× for a performance analysis tool that leverages our new analysis to recover program structure. © 2021 acm.

关键词： Graphic methods

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Generating local addresses and communication sets for data-parallel programs 93

Generating local addresses and communication sets for data-p...

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4th acm sigplan symposium on principles and practice of parallel programming, PPOPP 1993

作者： Chatterjee, Siddhartha Gilbert, John R. Long, Fred J.E. Schreiber, Robert Teng, Shang-Hua Research Institute for Advanced Computer Science Mail Stop T045-1 NASA Ames Research Center Moffett FieldCA94035-1000 United States Xerox Palo Alto Research Center 3333 Coyote Hill Road Palo AltoCA943041314 United States Department of Computer and Information Science University of California Santa CruzCA95064 United States Department of Mathematics Massachusetts Institute of Technology CambridgeMA02139 United States

ISBN: (纸本)0897915895

Generating local addresses and communication sets is an important issue in distributed-memory implementations of data-parallel languages such as High Performance Fortran. We show that for an array A affinely aligned to a template that is distributed across p processors with a cyclic(κ) distribution, and a computation involving the regular section A(: h: s), the local memory access sequence for any processor is characterized by a finite state machine of at most κ;states. We present fast algorithms for computing the essential information about these state machines, and extend the framework to handle multidimensional arrays. We also show how to generate communication sets using the state machine approach. Performance results show that this solution requires very little runtime overhead and acceptable preprocessing time.

关键词： Memory architecture

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Using multiple energy gears in MPI programs on a power-scalable cluster 05

Using multiple energy gears in MPI programs on a power-scala...

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2005 acm sigplan symposium on principles and Practise of parallel programming, PROPP 05

作者： Freeh, Vincent W. Pan, Feng Kappiah, Nandini Lowenthal, David K. Department of Computer Science North Carolina State University Raleigh NC United States Department of Computer Science University of Georgia Athens GA United States

ISBN: (纸本)9781595930804

Recently, system architects have built low-power, high-performance clusters, such as Green Destiny. the idea behind these clusters is to improve the energy efficiency of nodes. However, these clusters save power at the expense of performance. Our approach is instead to use high-performance cluster nodes that are frequency-and voltage-scalable;energy can than be saved by scaling down the CPU. Our prior work has examined the costs and benefits of executing an entire application at a single reduced frequency. this paper presents a framework for executing a single application in several frequency-voltage settings. the basic idea is to first divide programs into phases and then execute a series of experiments, with each phase assigned a prescribed frequency. During each experiment, we measure energy consumption and time and then use a heuristic to choose the assignment of frequency to phase for the next experiment. Our results show that significant energy can be saved without an undue performance penalty;particularly, our heuristic finds assignments of frequency to phase that is superior to any fixed-frequency solution. Specifically, this paper shows that more than half of the NAS benchmarks exhibit a better energy-time tradeoff using multiple gears than using a single gear. For example, IS using multiple gears uses 9% less energy and executes in 1% less time than the closest single-gear solution. Compared to no frequency scaling, multiple gear IS uses 16% less energy while executing only 1% longer. Copyright 2005 acm.

关键词： Computer programming

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ARMI: An adaptive, platform independent communication library

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acm sigplan NOTICES 2003年第10期38卷 229-240页

作者： Saunders, S Rauchwerger, L Texas A&M Univ Dept Comp Sci College Stn TX 77843 USA

ARMI is a communication library that provides a framework for expressing fine-grain parallelism and mapping it to a particular machine using shared-memory and message passing library calls. the library is an advanced implementation of the RMI protocol and handles low-level details such as scheduling incoming communication and aggregating outgoing communication to coarsen parallelism when necessary. these details can be tuned for different platforms to allow user codes to achieve the highest performance possible without manual modification. ARMI is used by STAPL, our generic parallel library, to provide a portable, user transparent communication layer, We present the basic design as well as the mechanisms used in the current Pthreads/OpenMP, MPI implementations and/or a combination thereof. Performance comparisons between ARMI and explicit use of Pthreads or MPI are given on a variety of machines, including an HP V2200, SGI Origin 3800, IBM Regatta-HPC and IBM RS6000 SP cluster.

关键词： languages RMI MPI pthreads OpenMP RPC run-time system communication library parallel programming

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Training one DeePMD Model in Minutes: a Step towards Online Learning 24

Training one DeePMD Model in Minutes: a Step towards Online ...

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29th acm sigplan Annual symposium on principles and practice of parallel programming (PPoPP)

作者： Hu, Siyu Zhao, Tong Sha, Qiuchen Li, Enji Meng, Xiangyu Liu, Liping Wang, Lin-Wang Tan, Guangming Jia, Weile Chinese Acad Sci Inst Comp Technol State Key Lab Proc Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China China Univ Petr Qingdao Inst Software Coll Comp Sci & Technol Qingdao Peoples R China Chinese Acad Sci Inst Semicond Beijing Peoples R China

ISBN: (纸本)9798400704352

Neural Network Molecular Dynamics (NNMD) has become a major approach in material simulations, which can speedup the molecular dynamics (MD) simulation for thousands of times, while maintaining ab initio accuracy, thus has a potential to fundamentally change the paradigm of material simulations. However, there are two time-consuming bottlenecks of the NNMD developments. One is the data access of ab initio calculation results. the other, which is the focus of the current work, is reducing the training time of NNMD model. the training of NNMD model is different from most other neural network training because the atomic force (which is related to the gradient of the network) is an important physical property to be fit. Tests show the traditional stochastic gradient methods, like the Adam algorithms, cannot efficiently deploy the multisample minibatch algorithm. As a result, a typical training (taking the Deep Potential Molecular Dynamics (DeePMD) as an example) can take many hours. In this work, we designed a heuristic minibatch quasi-Newtonian optimizer based on Extended Kalman Filter method. An early reduction of gradient and error is adopted to reduce memory footprint and communication. the memory footprint, communication and settings of hyper-parameters of this new method are analyzed in detail. Computational innovations such as customized kernels of the symmetry-preserving descriptor are applied to exploit the computing power of the heterogeneous architecture. Experiments are performed on 8 different datasets representing different real case situations, and numerical results show that our new method has an average speedup of 32.2 compared to the Reorganized Layer-wised Extended Kalman Filter with 1 GPU, reducing the absolute training time of one DeePMD model from hours to several minutes, making it one step toward online training.

关键词： parallel training Molecular dynamics First principle ab initio GPU

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