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User-controllable coherence for high performance shared memory multiprocessors

acm sigplan NOTICES 2003年第10期38卷 73-83页

作者： McCurdy, C Fischer, C Univ Wisconsin Dept Comp Sci Madison WI 53706 USA

In programming high performance applications, shared address-space platforms are preferable for fine-grained computation, while distributed address-space platforms are more suitable for coarse-grained computation. However, currently only distributed address-space systems scale beyond the low hundreds of processors. In this paper we introduce a hybrid architecture that allows users to trade off local memory usage for coherence communication, making possible larger-scale shared memory architectures. We introduce a programming model and examine possible implementations of hardware mechanisms, evaluating some of the trade-offs inherent in each. Preliminary experiments on an application with particularly fine-grained communication requirements indicate that effective placement of directives can reduce coherence communication by more than a factor of 10 for 64 processors.

关键词： performance design languages parallel computation shared memory architectures distributed memory architectures irregular computation

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Exploring the Use of WebAssembly in HPC 23

Exploring the Use of WebAssembly in HPC

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28th acm sigplan Annual symposium on principles and practice of parallel programming, PPoPP 2023

作者： Chadha, Mohak Krueger, Nils John, Jophin Jindal, Anshul Gerndt, Michael Benedict, Shajulin Computer Architecture and Parallel Systems Technische Universität München Germany Department of Computer Science and Engg. Indian and Institute of Information Technology Kottayam Kerala India

ISBN: (纸本)9798400700156

Containerization approaches based on namespaces offered by the Linux kernel have seen an increasing popularity in the HPC community both as a means to isolate applications and as a format to package and distribute them. However, their adoption and usage in HPC systems faces several challenges. these include difficulties in unprivileged running and building of scientific application container images directly on HPC resources, increasing heterogeneity of HPC architectures, and access to specialized networking libraries available only on HPC systems. these challenges of container-based HPC application development closely align with the several advantages that a new universal intermediate binary format called WebAssembly (Wasm) has to offer. these include a lightweight userspace isolation mechanism and portability across operating systems and processor architectures. In this paper, we explore the usage of Wasm as a distribution format for MPI-based HPC applications. To this end, we present MPIWasm, a novel Wasm embedder for MPI-based HPC applications that enables high-performance execution of Wasm code, has low-overhead for MPI calls, and supports high-performance networking interconnects present on HPC systems. We evaluate the performance and overhead of MPIWasm on a production HPC system and AWS Graviton2 nodes using standardized HPC benchmarks. Results from our experiments demonstrate that MPIWasm delivers competitive native application performance across all scenarios. Moreover, we observe that Wasm binaries are 139.5x smaller on average as compared to the statically-linked binaries for the different standardized benchmarks. © 2023 acm.

关键词： Containers

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Scalable parallel Minimum Spanning Forest Computation

Scalable Parallel Minimum Spanning Forest Computation

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17th acm sigplan symposium on principles and practice of parallel programming

作者： Nobari, Sadegh Cao, thanh-Tung Karras, Panagiotis Bressan, Stephane Natl Univ Singapore Singapore Singapore Rutgers State Univ Piscataway NJ 08855 USA

the proliferation of data in graph form calls for the development of scalable graph algorithms that exploit parallel processing environments. One such problem is the computation of a graph's minimum spanning forest (MSF). Past research has proposed several parallel algorithms for this problem, yet none of them scales to large, high-density graphs. In this paper we propose a novel, scalable, parallel MSF algorithm for undirected weighted graphs. Our algorithm leverages Prim's algorithm in a parallel fashion, concurrently expanding several subsets of the computed MSF. Our effort focuses on minimizing the communication among different processors without constraining the local growth of a processor's computed subtree. In effect, we achieve a scalability that previous approaches lacked. We implement our algorithm in CUDA, running on a GPU and study its performance using real and synthetic, sparse as well as dense, structured and unstructured graph data. Our experimental study demonstrates that our algorithm outperforms the previous state-of-the-art GPU-based MSF algorithm, while being several order of magnitude faster than sequential CPU-based algorithms.

关键词： Algorithms Experimentation Performance parallel Graph Algorithms Minimum Spanning Forest GPU

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Using thread-level speculation to simplify manual parallelization

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acm sigplan NOTICES 2003年第10期38卷 1-12页

作者： Prabhu, MK Olukotun, K Stanford Univ Comp Syst Lab Stanford CA 94305 USA

In this paper, we provide examples of how thread-level speculation (TLS) simplifies manual parallelization and enhances its performance. A number of techniques for manual parallelization using TLS are presented and results are provided that indicate the performance contribution of each technique on seven SPEX CPU2000 benchmark applications. We also provide indications of the programming effort required to parallelize each benchmark. TLS parallelization yielded a 110% speedup on our four floating point applications and a 70% speedup on our three integer applications, while requiring only approximately 80 programmer hours and 150 lines of non-template code per application. these results support the idea that manual parallelization using TLS is an efficient way to extract fine-grain thread-level parallelism.

关键词： design algorithms performance measurement chip multiprocessor data speculation manual parallel programming multithreading feedback-driven optimization

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A hierarchical approach to reducing communication in parallel graph algorithms 2015

A hierarchical approach to reducing communication in paralle...

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20th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2015

作者： Harshvardhan Amato, Nancy M. Rauchwerger, Lawrence Parasol Laboratory Department of Computer Science and Engineering Texas A and M University United States

ISBN: (纸本)9781450332057

Large-scale graph computing has become critical due to the ever-increasing size of data. However, distributed graph computations are limited in their scalability and performance due to the heavy communication inherent in such computations. this is exacerbated in scale-free networks, such as social and web graphs, which contain hub vertices that have large degrees and therefore send a large number of messages over the network. Furthermore, many graph algorithms and computations send the same data to each of the neighbors of a vertex. Our proposed approach recognizes this, and reduces communication performed by the algorithm without change to user-code, through a hierarchical machine model imposed upon the input graph. the hierarchical model takes advantage of locale information of the neighboring vertices to reduce communication, both in message volume and total number of bytes sent. It is also able to better exploit the machine hierarchy to further reduce the communication costs, by aggregating traffic between different levels of the machine hierarchy. Results of an implementation in the STAPL GL shows improved scalability and performance over the traditional level-synchronous approach, with 2.5 × - 8× improvement for a variety of graph algorithms at 12, 000+ cores.

关键词： Big data

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Training one DeePMD Model in Minutes: a Step towards Online Learning 24

Training one DeePMD Model in Minutes: a Step towards Online ...

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29th acm sigplan Annual symposium on principles and practice of parallel programming (PPoPP)

作者： Hu, Siyu Zhao, Tong Sha, Qiuchen Li, Enji Meng, Xiangyu Liu, Liping Wang, Lin-Wang Tan, Guangming Jia, Weile Chinese Acad Sci Inst Comp Technol State Key Lab Proc Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China China Univ Petr Qingdao Inst Software Coll Comp Sci & Technol Qingdao Peoples R China Chinese Acad Sci Inst Semicond Beijing Peoples R China

ISBN: (纸本)9798400704352

Neural Network Molecular Dynamics (NNMD) has become a major approach in material simulations, which can speedup the molecular dynamics (MD) simulation for thousands of times, while maintaining ab initio accuracy, thus has a potential to fundamentally change the paradigm of material simulations. However, there are two time-consuming bottlenecks of the NNMD developments. One is the data access of ab initio calculation results. the other, which is the focus of the current work, is reducing the training time of NNMD model. the training of NNMD model is different from most other neural network training because the atomic force (which is related to the gradient of the network) is an important physical property to be fit. Tests show the traditional stochastic gradient methods, like the Adam algorithms, cannot efficiently deploy the multisample minibatch algorithm. As a result, a typical training (taking the Deep Potential Molecular Dynamics (DeePMD) as an example) can take many hours. In this work, we designed a heuristic minibatch quasi-Newtonian optimizer based on Extended Kalman Filter method. An early reduction of gradient and error is adopted to reduce memory footprint and communication. the memory footprint, communication and settings of hyper-parameters of this new method are analyzed in detail. Computational innovations such as customized kernels of the symmetry-preserving descriptor are applied to exploit the computing power of the heterogeneous architecture. Experiments are performed on 8 different datasets representing different real case situations, and numerical results show that our new method has an average speedup of 32.2 compared to the Reorganized Layer-wised Extended Kalman Filter with 1 GPU, reducing the absolute training time of one DeePMD model from hours to several minutes, making it one step toward online training.

关键词： parallel training Molecular dynamics First principle ab initio GPU

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parallel binary code analysis 21

Parallel binary code analysis

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26th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2021

作者： Meng, Xiaozhu Anderson, Jonathon M. Mellor-Crummey, John Krentel, Mark W. Miller, Barton P. Milaković, Sran Department of Computer Science Rice University Houston TX United States Computer Sciences Department University of Wisconsin-Madison MadisonWI United States

Binary code analysis is widely used to help assess a program9;s correctness, performance, and provenance. Binary analysis applications often construct control flow graphs, analyze data flow, and use debugging infor... 详细信息

ISBN: (纸本)9781450382946

Binary code analysis is widely used to help assess a program's correctness, performance, and provenance. Binary analysis applications often construct control flow graphs, analyze data flow, and use debugging information to understand how machine code relates to source lines, inlined functions, and data types. To date, binary analysis has been single-threaded, which is too slow for convenient use in performance tuning workflows where it is used to help attribute performance to complex applications with large binaries. this paper describes our design and implementation for accelerating the task of constructing control flow graphs (CFGs) from binaries by using multithreading. Prior research focuses on algorithms for analysis of challenging code constructs encountered while constructing CFGs, including functions sharing code, jump tables, non-returning functions, and tail calls. these algorithms are described from a program analysis perspective and are not suitable for direct parallel implementation. We abstract the task of constructing CFGs as repeated applications of several core CFG operations that include creating functions, basic blocks, and edges. We then derive CFG operation dependency, commutativity, and monotonicity. these operation properties guide our design of a new parallel analysis for constructing CFGs. Using 64 threads, we achieved as much as 25× speedup for constructing CFGs and 8× for a performance analysis tool that leverages our new analysis to recover program structure. © 2021 acm.

关键词： Graphic methods

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Using multiple energy gears in MPI programs on a power-scalable cluster 05

Using multiple energy gears in MPI programs on a power-scala...

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2005 acm sigplan symposium on principles and Practise of parallel programming, PROPP 05

作者： Freeh, Vincent W. Pan, Feng Kappiah, Nandini Lowenthal, David K. Department of Computer Science North Carolina State University Raleigh NC United States Department of Computer Science University of Georgia Athens GA United States

ISBN: (纸本)9781595930804

Recently, system architects have built low-power, high-performance clusters, such as Green Destiny. the idea behind these clusters is to improve the energy efficiency of nodes. However, these clusters save power at the expense of performance. Our approach is instead to use high-performance cluster nodes that are frequency-and voltage-scalable;energy can than be saved by scaling down the CPU. Our prior work has examined the costs and benefits of executing an entire application at a single reduced frequency. this paper presents a framework for executing a single application in several frequency-voltage settings. the basic idea is to first divide programs into phases and then execute a series of experiments, with each phase assigned a prescribed frequency. During each experiment, we measure energy consumption and time and then use a heuristic to choose the assignment of frequency to phase for the next experiment. Our results show that significant energy can be saved without an undue performance penalty;particularly, our heuristic finds assignments of frequency to phase that is superior to any fixed-frequency solution. Specifically, this paper shows that more than half of the NAS benchmarks exhibit a better energy-time tradeoff using multiple gears than using a single gear. For example, IS using multiple gears uses 9% less energy and executes in 1% less time than the closest single-gear solution. Compared to no frequency scaling, multiple gear IS uses 16% less energy while executing only 1% longer. Copyright 2005 acm.

关键词： Computer programming

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Exploiting task-level concurrency in a programmable network interface

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acm sigplan NOTICES 2003年第10期38卷 61-72页

作者： Kim, HY Pai, VS Rixner, S Rice Univ Houston TX 77251 USA

Programmable network interfaces provide the potential to extend the functionality of network services but lead to instruction processing overheads when compared to application-specific network interfaces. this paper aims to offset those performance disadvantages by exploiting task-level concurrency in the workload to parallelize the network interface firmware for a programmable controller with two processors. By carefully partitioning the handler procedures that process various events related to the progress of a packet, the system can minimize sharing, achieve load balance, and efficiently utilize on-chip storage. Compared to the uniprocessor firmware released by the manufacturer, the parallelized network interface firmware increases throughput by 65% for bidirectional UDP traffic of maximum-sized packets, 157% for bidirectional UDP traffic of minimum-sized packets, and 32-107% for real network services. this parallelization results in performance within 10-20% of a modem ASIC-based network interface for real network services.

关键词： experimentation, performance programmable network interface parallel programming ethernet firmware

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Generating local addresses and communication sets for data-parallel programs 93

Generating local addresses and communication sets for data-p...

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4th acm sigplan symposium on principles and practice of parallel programming, PPOPP 1993

作者： Chatterjee, Siddhartha Gilbert, John R. Long, Fred J.E. Schreiber, Robert Teng, Shang-Hua Research Institute for Advanced Computer Science Mail Stop T045-1 NASA Ames Research Center Moffett FieldCA94035-1000 United States Xerox Palo Alto Research Center 3333 Coyote Hill Road Palo AltoCA943041314 United States Department of Computer and Information Science University of California Santa CruzCA95064 United States Department of Mathematics Massachusetts Institute of Technology CambridgeMA02139 United States

ISBN: (纸本)0897915895

Generating local addresses and communication sets is an important issue in distributed-memory implementations of data-parallel languages such as High Performance Fortran. We show that for an array A affinely aligned to a template that is distributed across p processors with a cyclic(κ) distribution, and a computation involving the regular section A(: h: s), the local memory access sequence for any processor is characterized by a finite state machine of at most κ;states. We present fast algorithms for computing the essential information about these state machines, and extend the framework to handle multidimensional arrays. We also show how to generate communication sets using the state machine approach. Performance results show that this solution requires very little runtime overhead and acceptable preprocessing time.

关键词： Memory architecture

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