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Phoenix: a parallel programming model for accommodating dynamically joining/leaving resources

acm sigplan NOTICES 2003年第10期38卷 215-228页

作者： Taura, K Kaneda, K Endo, T Yonezawa, A Univ Tokyo Bunkyo Ku Tokyo 1130033 Japan PRESTO JST Kawaguchi Saitama 3320012 Japan

this paper proposes Phoenix, a programming model for writing parallel and distributed applications that accommodate dynamically joining/leaving compute resources. In the proposed model, nodes involved in an application see a large and fixed virtual node name space. they communicate via messages, whose destinations are specified by virtual node names, rather than names bound to a physical resource. We describe Phoenix API and show how it allows a transparent migration of application states, as well as dynamically joining/leaving nodes as its by-product. We also demonstrate through several application studies that Phoenix model is close enough to regular message passing, thus it is a general programming model that facilitates porting many parallel applications/algorithms to more dynamic environments. Experimental results indicate applications that have a small task migration cost can quickly take advantage of dynamically joining resources using Phoenix. Divide-and-conquer algorithms written in Phoenix achieved a good speedup with a large number of nodes across multiple LANs (120 times speedup using 169 CPUs across three LANs). We believe Phoenix provides a useful programming abstraction and platform for emerging parallel applications that must be deployed across multiple LANs and/or shared clusters having dynamically varying resource conditions.

关键词： performance parallel programming distributed programming message passing migration resource reconfiguration

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Exploiting task-level concurrency in a programmable network interface

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acm sigplan NOTICES 2003年第10期38卷 61-72页

作者： Kim, HY Pai, VS Rixner, S Rice Univ Houston TX 77251 USA

Programmable network interfaces provide the potential to extend the functionality of network services but lead to instruction processing overheads when compared to application-specific network interfaces. this paper aims to offset those performance disadvantages by exploiting task-level concurrency in the workload to parallelize the network interface firmware for a programmable controller with two processors. By carefully partitioning the handler procedures that process various events related to the progress of a packet, the system can minimize sharing, achieve load balance, and efficiently utilize on-chip storage. Compared to the uniprocessor firmware released by the manufacturer, the parallelized network interface firmware increases throughput by 65% for bidirectional UDP traffic of maximum-sized packets, 157% for bidirectional UDP traffic of minimum-sized packets, and 32-107% for real network services. this parallelization results in performance within 10-20% of a modem ASIC-based network interface for real network services.

关键词： experimentation, performance programmable network interface parallel programming ethernet firmware

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Compactly representing parallel program executions

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acm sigplan NOTICES 2003年第10期38卷 190-201页

作者： Goel, A Roychoudhury, A Mitra, T Natl Univ Singapore Sch Comp Singapore 117543 Singapore

Collecting a program9;s execution profile is important for many reasons: code optimization, memory layout, program debugging and program comprehension. Path based execution profiles are more detailed than count bas... 详细信息

Collecting a program's execution profile is important for many reasons: code optimization, memory layout, program debugging and program comprehension. Path based execution profiles are more detailed than count based execution profiles, since they present the order of execution of the various blocks in a program: modules, procedures, basic blocks etc. Recently, online string compression techniques have been employed for collecting compact representations of sequential program executions. In this paper, we show how a similar approach can be taken for shared memory parallel programs. Our compaction scheme yields one to two orders of magnitude compression compared to the uncompressed parallel program trace on some of the SPLASH benchmarks. Our compressed execution traces contain detailed information about synchronization and control/data flow which can be exploited for post-mortem analysis. In particular, information in our compact execution traces are useful for accurate data race detection (detecting unsynchronized shared variable accesses that occurred in the execution).

关键词： algorithms measurement path profiling program path compression dynamic program analysis

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Architectural Support for Cilk Computations on Many-core Architectures

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acm sigplan NOTICES 2009年第4期44卷 285-286页

作者： Long, Guoping Fan, Dongrui Zhang, Junchao Chinese Acad Sci Inst Comp Technol Key Lab Comp Syst & Architecture Beijing 100864 Peoples R China

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NUMA-aware graph-structured analytics 2015

NUMA-aware graph-structured analytics

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20th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2015

作者： Zhang, Kaiyuan Chen, Rong Chen, Haibo Shanghai Key Laboratory of Scalable Computing and Systems Institute of Parallel and Distributed Systems Shanghai Jiao Tong University China

ISBN: (纸本)9781450332057

Graph-structured analytics has been widely adopted in a number of big data applications such as social computation, web-search and recommendation systems. though much prior research focuses on scaling graph-analytics on distributed environments, the strong desire on performance per core, dollar and joule has generated considerable interests of processing large-scale graphs on a single server-class machine, which may have several terabytes of RAM and 80 or more cores. However, prior graph-analytics systems are largely neutral to NUMA characteristics and thus have suboptimal performance. this paper presents a detailed study of NUMA characteristics and their impact on the efficiency of graph-analytics. Our study uncovers two insights: 1) either random or interleaved allocation of graph data will significantly hamper data locality and parallelism;2) sequential inter-node (i.e., remote) memory accesses have much higher bandwidth than both intra- and inter-node random ones. Based on them, this paper describes Polymer, a NUMA-aware graph-analytics system on multicore with two key design decisions. First, Polymer differentially allocates and places topology data, application-defined data and mutable runtime states of a graph system according to their access patterns to minimize remote accesses. Second, for some remaining random accesses, Polymer carefully converts random remote accesses into sequential remote accesses, by using lightweight replication of vertices across NUMA nodes. To improve load balance and vertex convergence, Polymer is further built with a hierarchical barrier to boost parallelism and locality, an edge-oriented balanced partitioning for skewed graphs, and adaptive data structures according to the proportion of active vertices. A detailed evaluation on an 80-core machine shows that Polymer often outperforms the state-of-the-art single-machine graph-analytics systems, including Ligra, X-Stream and Galois, for a set of popular real-world and synthetic grap

关键词： Random access storage

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A Domain-Specific Approach To Heterogeneous parallelism

A Domain-Specific Approach To Heterogeneous Parallelism

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16th acm symposium on principles and practice of parallel programming

作者： Chafi, Hassan Sujeeth, Arvind K. Brown, Kevin J. Lee, HyoukJoong Atreya, Anand R. Olukotun, Kunle Stanford Univ Pervas Parallelism Lab Stanford CA 94305 USA

Exploiting heterogeneous parallel hardware currently requires mapping application code to multiple disparate programming models. Unfortunately, general-purpose programming models available today can yield high performance but are too low-level to be accessible to the average programmer. We propose leveraging domain-specific languages (DSLs) to map high-level application code to heterogeneous devices. To demonstrate the potential of this approach we present OptiML, a DSL for machine learning. OptiML programs are implicitly parallel and can achieve high performance on heterogeneous hardware with no modification required to the source code. For such a DSL-based approach to be tractable at large scales, better tools are required for DSL authors to simplify language creation and parallelization. To address this concern, we introduce De lite, a system designed specifically for DSLs that is both a framework for creating an implicitly parallel DSL as well as a dynamic runtime providing automated targeting to heterogeneous parallel hardware. We show that OptiML running on De lite achieves single-threaded, parallel, and GPU performance superior to explicitly parallelized MATLAB code in nearly all cases.

关键词： parallel programming Domain-Specific Languages Dynamic Optimizations Languages Performance

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Boosting Performance and QoS for Concurrent GPU B+trees by Combining-Based Synchronization 23

Boosting Performance and QoS for Concurrent GPU B+trees by C...

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28th acm sigplan Annual symposium on principles and practice of parallel programming, PPoPP 2023

作者： Zhang, Weihua Zhao, Chuanlei Peng, Lu Lin, Yuzhe Zhang, Fengzhe Lu, Yunping School of Computer Science Fudan University China Institute of Big Data Fudan University China State Key Laboratory of Mathematical Engineering and Advanced Computing China Parallel Processing Institute Fudan University China Department of Computer Science Tulane University United States

ISBN: (纸本)9798400700156

Concurrent B+trees have been widely used in many systems. With the scale of data requests increasing exponentially, the systems are facing tremendous performance pressure. GPU has shown its potential to accelerate concurrent B+trees performance. When many concurrent requests are processed, the conflicts should be detected and resolved. Prior methods guarantee the correctness of concurrent GPU B+trees through lock-based or software transactional memory (STM)-based approaches. However, these methods complicate the request processing logic, increase the number of memory accesses and bring execution path divergence. they lead to performance degradation and variance in response time increasing. Moreover, previous methods do not guarantee linearizability among concurrent requests. In this paper, we design a combined-based concurrency control framework, called Eirene, for GPU B+tree to reduce the overhead of conflict detection and resolution. First, a combining-based synchronization method is designed to combine and issue requests. It combines the requests with the same key, constructs their dependence, decides the issued request, and determines their return values. Since only one request for each key is issued, key conflicts are eliminated. then, an optimistic STM method is used to reduce structure conflicts. the query and the update requests are partitioned into different kernels. For the update kernels, STM is involved only when the number of the retry reaches a threshold. Finally, a locality-aware warp reorganization optimization is proposed to improve memory behavior and reduce conflicts by exploiting the locality among requests. Evaluations on an NVIDIA A100 GPU show that Eirene is efficient (a throughput of 2.4 billion per second) and can guarantee linearizability. Compared to the state-of-the-art GPU B+tree, it can achieve a speedup of 7.43X and reduce the response time variance from 36% to 5%. © 2023 acm.

关键词： Graphics processing unit

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Array data-flow analysis and its use in array privatization 93

Array data-flow analysis and its use in array privatization

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20th Annual acm sigplan-SIGACT symposium on principles of programming Languages, POPL'93

作者： Maydan, Dror E. Amarasinghe, Saman P. Lam, Monica S. Stanford Univ CA United States

ISBN: (纸本)0897915607

Data-flow analysis of scalar variables and data dependence analysis on array elements are two important program analyses used in optimizing and parallelizing compilers. Traditional data-flow analysis models accesses of array elements simply as accesses to the entire array, and is inadequate for parallelizing loops in array-based programs. On the other hand, data dependence analysis differentiates between different array elements but is flow-insensitive. this paper studies the combination of these two analyses - data-flow analysis of accesses to individual array elements. the problem of finding precise array data-flow information in the domain of loop nests where the loop bounds and array indices are affine functions of loop indices was first formulated by Feautrier. Feautrier's algorithm, based on parametric integer programming techniques, is general but inefficient. this paper presents an efficient algorithm that can find the same precise information for many of the programs found in practice. In this paper, we argue that data-flow analysis of individual array elements is necessary for effective automatic parallelization. In particular, we demonstrate the use of array data-flow analysis in an important optimization known as array privatization. By demonstrating that array data-flow analysis can be computed efficiently and by showing the importance of the optimizations enabled by the analysis, this paper suggests that array data-flow analysis may become just as important in future optimizing and parallelizing compilers as data-flow and data dependence analysis are in today's compilers.

关键词： parallel processing systems

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Lifetime-Based Optimization for Simulating Quantum Circuits on a New Sunway Supercomputer 23

Lifetime-Based Optimization for Simulating Quantum Circuits ...

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28th acm sigplan Annual symposium on principles and practice of parallel programming, PPoPP 2023

作者： Chen, Yaojian Liu, Yong Shi, Xinmin Song, Jiawei Liu, Xin Gan, Lin Guo, Chu Fu, Haohuan Gao, Jie Chen, Dexun Yang, Guangwen Tsinghua University Beijing China National Supercomputing Center in Wuxi Zhejiang Lab Hangzhou China Information Engineering University Zhengzhou China National Supercomputing Center in Wuxi China Tsinghua University National Supercomputing Center in Wuxi China National Research Centre of Parallel Engineering and Technology Beijing China Tsinghua University National Supercomputing Center in Wuxi Zhejiang Lab Hangzhou China

ISBN: (纸本)9798400700156

High-performance classical simulator for quantum circuits, in particular the tensor network contraction algorithm, has become an important tool for the validation of noisy quantum computing. In order to address the memory limitations, the slicing technique is used to reduce the tensor dimensions, but it could also lead to additional computation overhead that greatly slows down the overall performance. this paper proposes novel lifetime-based methods to reduce the slicing overhead and improve the computing efficiency, including, an interpretation method to deal with slicing overhead, an inplace slicing strategy to find the smallest slicing set and an adaptive tensor network contraction path refiner customized for Sunway architecture. Experiments show that in most cases the slicing overhead with our inplace slicing strategy would be less than the Cotengra, which is the most used graph path optimization software at present. Finally, the resulting simulation time is reduced to 96.1s for the Sycamore quantum processor RQC, with a sustainable single-precision performance of 308.6Pflops using over 41M cores to generate 1M correlated samples, which is more than 5 times performance improvement compared to 60.4 Pflops in 2021 Gordon Bell Prize work. © 2023 Owner/Author.

关键词： Timing circuits

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A Peta-scalable CPU-GPU Algorithm for Global Atmospheric Simulations 13

A Peta-scalable CPU-GPU Algorithm for Global Atmospheric Sim...

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18th acm sigplan symposium on principles and practice of parallel programming

作者： Yang, Chao Xue, Wei Fu, Haohuan Gan, Lin Li, Linfeng Xu, Yangtong Lu, Yutong Sun, Jiachang Yang, Guangwen Zheng, Weimin Chinese Acad Sci Inst Software Beijing Peoples R China Tsinghua Univ Dept Comp Sci & Technol Beijing 100084 Peoples R China Tsinghua Univ Minist Educ Key Lab Earth Syst Modeling Beijing 100084 Peoples R China Tsinghua Univ Ctr Earth Syst Sci Beijing 100084 Peoples R China Natl Univ Def Technol Dept Comp Sci & Technol Changsha Hunan Peoples R China Chinese Acad Sci State Key Lab Space Weather Beijing Peoples R China

ISBN: (纸本)9781450319225

Developing highly scalable algorithms for global atmospheric modeling is becoming increasingly important as scientists inquire to understand behaviors of the global atmosphere at extreme scales. Nowadays, heterogeneous architecture based on both processors and accelerators is becoming an important solution for large-scale computing. However, large-scale simulation of the global atmosphere brings a severe challenge to the development of highly scalable algorithms that fit well into state-of-the-art heterogeneous systems. Although successes have been made on GPU-accelerated computing in some top-level applications, studies on fully exploiting heterogeneous architectures in global atmospheric modeling are still very less to be seen, due in large part to both the computational difficulties of the mathematical models and the requirement of high accuracy for long term simulations. In this paper, we propose a peta-scalable hybrid algorithm that is successfully applied in a cubed-sphere shallow-water model for global atmospheric simulations. We employ an adjustable partition between CPUs and GPUs to achieve a balanced utilization of the entire hybrid system, and present a pipe-flow scheme to conduct conflict-free inter-node communication on the cubed-sphere geometry and to maximize communication-computation overlap. Systematic optimizations for multithreading on both GPU and CPU sides are performed to enhance computing throughput and improve memory efficiency. Our experiments demonstrate nearly ideal strong and weak scalabilities on up to 3,750 nodes of the Tianhe-1A. the largest run sustains a performance of 0.8 Pflops in double precision (32% of the peak performance), using 45,000 CPU cores and 3,750 GPUs.

关键词： parallel algorithm atmospheric modeling GPU heterogeneous system communication-computation overlap scalability

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