the size and complexity of large-scale distributed embedded systems such as automotive and process controls have increased recently. Sophisticated systems that are safe and environmentally friendly require numerous ty...
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the size and complexity of large-scale distributed embedded systems such as automotive and process controls have increased recently. Sophisticated systems that are safe and environmentally friendly require numerous types of sensor data, which are collected from various devices and sent to computers through networks. To develop such large-scale distributed embedded systems with high dependability and productivity, we have developed a virtual execution environment platform. this platform integrates numerous CPU simulators and various device simulators through the network and provides network-wide simulation functionalities. In this paper, we describe a fast CPU simulator and controlled object simulation for testing control software in a virtual software execution environment. the virtual environment integrates a CPU simulator and a controlled object simulator in order to test functional behaviors of embedded control software. the environment enables the developer to test control software at the same execution rate as a real system without the source codes. this is very helpful because in this industry, not all of the source codes are provided.
Many applications in the industrial control domain are safety-critical. A large number of analysis techniques to guarantee safety may be applied at different levels in the development process of a Programmable Logic C...
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Many applications in the industrial control domain are safety-critical. A large number of analysis techniques to guarantee safety may be applied at different levels in the development process of a Programmable Logic Controller. the development process is typically associated with a tool chain comprising model transformations. the preservation of safety properties in model transformations is necessary to achieve a safe system. Preservation can be guaranteed by showing that invariants are preserved by transformations. Adequate transformation rules and invariant specification mechanisms are needed for this. We report on a transformation from Sequential Function Charts and Function Block Diagrams of the IEC 61131-3 standard to BIP. Our presentation features a description of formal syntax and semantics of the involved languages. We present transformation rules for generating BIP code out of IEC 61131-3 specifications. Based on this, we establish a notion of invariant preservation between the two languages.
Achieving situation awareness is especially challenging for real-time data stream applications because they i) operate on continuous unbounded streams of data, and ii) have inherent real-time requirements. In this pap...
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Achieving situation awareness is especially challenging for real-time data stream applications because they i) operate on continuous unbounded streams of data, and ii) have inherent real-time requirements. In this paper we show how formal data stream modeling and analysis can be used to better understand stream behavior, evaluate query costs, and improve application performance. We use MEDAL, a formal specification language based on Petri nets, to model the data stream queries and the Quality-of-Service (QoS) management mechanisms in a data stream system. MEDAL's ability to combine query logic and data admission control in one model allows us to design a single comprehensive model of the system. this model can be used to perform a large set of analyses to help improve the application's performance and QoS.
AUTOSAR (Automotive Open System Architecture) is enjoying increasing interest and broad acceptance in the automotive domain. AUTOSAR aims at defining an open standardized software architecture to face future challenge...
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AUTOSAR (Automotive Open System Architecture) is enjoying increasing interest and broad acceptance in the automotive domain. AUTOSAR aims at defining an open standardized software architecture to face future challenges in automotive development including the development of time-critical systems (e.g. brake-by-wire or steer-by-wire). Mastering the development of such systems requires being able to analyze their real-time behavior. Scheduling analysis is the theory that studies how far a real-time system may satisfy its real-time requirements against its real-time properties. In this paper, we will study to what extent it is possible to apply some of those scheduling analysis techniques on real-time systems deployed on AUTOSAR-compliant architectures. the paper focuses on scheduling analysis techniques implemented in one open source tool. A concrete case study shows the feasibility of the approach and shows scheduling analysis results.
In this paper we are interested in mixed-criticality embedded real-time applications mapped on distributed heterogeneous architectures. the architecture provides both spatial and temporal partitioning, thus enforcing ...
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In this paper we are interested in mixed-criticality embedded real-time applications mapped on distributed heterogeneous architectures. the architecture provides both spatial and temporal partitioning, thus enforcing enough separation for the critical applications. With temporal partitioning, each application is allowed to run only within predefined time slots, allocated on each processor. the sequence of time slots for all the applications on a processor are grouped within a Major Frame, which is repeated periodically. We assume that the safety-critical applications (on all criticality levels) are scheduled using static-cyclic scheduling and the non-critical applications are scheduled using fixed-priority preemptive scheduling. We consider that each application runs in a separate partition, and each partition is allocated several time slots on the processors where the application is mapped. We are interested to determine the sequence and size of the time slots within the Major Frame on each processor such that boththe safety-critical and non-critical applications are schedulable. We have proposed a Simulated Annealing-based approach to solve this optimization problem. the proposed algorithm has been evaluated using several synthetic and real-life benchmarks.
To avoid data cache trashing between heap-allocated data and other data areas, a distinct object cache has been proposed for embedded real-time Java processors. this object cache uses high associativity in order to st...
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To avoid data cache trashing between heap-allocated data and other data areas, a distinct object cache has been proposed for embedded real-time Java processors. this object cache uses high associativity in order to statically track different object pointers for worst-case execution-time analysis. However, before implementing such an object cache, an empirical analysis of different organization forms is needed. We use a cross-profiling technique based on aspect-oriented programming in order to evaluate different object cache organizations with standard Java benchmarks. From the evaluation we conclude that field access exhibits some temporal locality, but almost no spatial locality. therefore, filling long cache lines on a miss just introduces a high miss penalty without increasing the hit rate enough to make up for the increased miss penalty. For an object cache, it is more efficient to fill individual words within the cache line on a miss.
Worst Case Execution time (WCET) computation is crucial to the overall timing analysis of real-time embedded systems. Facing the ever increasing complexity of such systems, techniques dedicated to WCET analysis can ta...
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Worst Case Execution time (WCET) computation is crucial to the overall timing analysis of real-time embedded systems. Facing the ever increasing complexity of such systems, techniques dedicated to WCET analysis can take advantage of component Based Software Engineering (CBSE) by decomposing a difficult problem into smaller pieces, easier to analyse. To achieve this objective, the corresponding analysis results have to be composed to provide timing guarantees on the whole system. In this paper, we express the WCET of a component as a formula, allowing to represent its different computational modes. We then propose a Model Driven Engineering (MDE) approach that derives parametric WCET for composite components from parametric WCET of their subcomponents. this approach gives more accurate WCET estimates than naaive additive compositional analysis by taking into account usage context of components. However, analysis scalability concerns lead us to consider a trade-off between precision and scalability. this trade-off can be specified in the model. the composition of WCET estimations is automated and produces the parametric WCET expression of the composite component under analysis. this approach has been integrated in PRIDE.
Type-safe high-level languages such as Java have not yet found their way into the domain of deeply embedded systems, even though numerous attempts have been made to make these languages cost attractive. One major chal...
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Type-safe high-level languages such as Java have not yet found their way into the domain of deeply embedded systems, even though numerous attempts have been made to make these languages cost attractive. One major challenge that remains is the huge existing code base in many industries. Completely reengineering this code base is not viable for cost and time reasons. We present an approach that allows to isolatedly combine legacy software components and safe software components in an embedded system using the two most common communication idioms found in this domain. Our approach allows the developer to freely choose between hardware- and software-based isolation mechanisms. We demonstrate the feasibility of our approach by porting a non-trivial part of a real-world, hard real-time embedded avionics application. Our results show that the cost of this mixed-mode operation is on the same scale as the pure operation.
Multicore processors can deliver higher performance than single-core processors by exploiting thread level parallelism (TLP): applications are split into independent threads, each of which is mapped into a different c...
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Multicore processors can deliver higher performance than single-core processors by exploiting thread level parallelism (TLP): applications are split into independent threads, each of which is mapped into a different core, reducing the execution time and potentially its worst-case execution time (WCET). Unfortunately, inter-thread interferences generated by simultaneous accesses to shared resources from different threads may completely destroy the performance benefits brought by TLP. this paper proposes a software/hardware cache partitioning approach that reduces the inter-thread memory interferences generated in hard real-time software-pipelined parallel applications. Our results show that our approach effectively reduces memory interferences, while still guaranteeing a predictable timing behaviour, achieving a WCET estimation reduction of 28% for a software pipelined version of the LU decomposition application with respect to the single-threaded version.
One cannot image today9;s life without mechatronic systems, which have to be developed in a joint effort by teams of mechanical engineers, electrical engineers, control engineers and software engineers. Often these...
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One cannot image today's life without mechatronic systems, which have to be developed in a joint effort by teams of mechanical engineers, electrical engineers, control engineers and software engineers. Often these systems are applied in safety critical environments like in cars or aircrafts. this requires systems that function correctly and do not cause hazardous situations. However, random errors due to wear or external influences cannot be completely excluded. Consequently, we have to perform a hazard analysis for the system. Further, the union of four disciplines in one system requires the development and analysis of the system as a whole. We present a component-based hazard analysis that considers the entire mechatronic system including hardware, i.e. mechanical and electrical components, and software components. Our approach considers the physical properties of different types of flow in mechatronic systems. We have identified reusable patterns for the failure behavior which can be generated automatically. this reduces the effort for the developer. As cycles, e.g. control cycles, are an internal part of every mechatronic system our approach is able to handle cycles. the presented approach has been applied to a real-life case study.
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