We present a survey on the academic and industrial structured ASIC practices, especially focusing on the test strategies currently in use. then, we compare two possible test generation flows, underlining the most crit...
详细信息
ISBN:
(纸本)1424401844
We present a survey on the academic and industrial structured ASIC practices, especially focusing on the test strategies currently in use. then, we compare two possible test generation flows, underlining the most critical aspects introduced by the adoption of the structured ASIC methodology.
this paper presents a scalable asynchronous dataflow processor. the main idea of the presented processor architecture is that the processing elements (PEs) are intelligent and can communicate directly with each other....
详细信息
ISBN:
(纸本)1424401844
this paper presents a scalable asynchronous dataflow processor. the main idea of the presented processor architecture is that the processing elements (PEs) are intelligent and can communicate directly with each other. A control element (CE) is used to solve possible conflicts between the data transferring of PEs and to control the execution of the program.
this paper presents a new, patent pending, random bit generator whose noise source exploits the leakage current in a reverse biased p-n junction. the circuit is described and a model is provided to estimate data-rate ...
详细信息
ISBN:
(纸本)1424401844
this paper presents a new, patent pending, random bit generator whose noise source exploits the leakage current in a reverse biased p-n junction. the circuit is described and a model is provided to estimate data-rate and expected quality of the generated bit sequence. Since the noise source is quasi-stateless, its deterministic evolution does not present complex patterns and therefore a lack of entropy and faults can be detected on-line.
Hardware accelerators for H.264/AVC using arithmetic coding require special approaches to achieve high throughputs. this paper proposes an efficient architecture for the context formatter that is a part of the H.264/A...
详细信息
ISBN:
(纸本)1424401844
Hardware accelerators for H.264/AVC using arithmetic coding require special approaches to achieve high throughputs. this paper proposes an efficient architecture for the context formatter that is a part of the H.264/AVC binary encoder. Five versions of the architecture are developed to match different throughputs. the implementation results show that the proposed versions of the context formatter match the performance of corresponding arithmetic coders.
In current hardware design flow, functional verification is widely acknowledged as the crucial step. this paper presents a new contribution to reduce the cost of this step by automating it. We address here, one of the...
详细信息
ISBN:
(纸本)1424401844
In current hardware design flow, functional verification is widely acknowledged as the crucial step. this paper presents a new contribution to reduce the cost of this step by automating it. We address here, one of the principal challenges of dynamic verification, by providing a new approach for automatic test generation. this approach combines mutation-based test techniques and genetic algorithms to produce stimuli for design under test. the feasibility of the proposed approach is assessed with a preliminary implementation, and some framework has been tested.
Polymorphic gates exhibit one or more additional functions in addition to the "main" function of the gate. the additional functions can be activated under certain conditions by changing control parameters (s...
详细信息
ISBN:
(纸本)1424401844
Polymorphic gates exhibit one or more additional functions in addition to the "main" function of the gate. the additional functions can be activated under certain conditions by changing control parameters (such as temperature, Vdd, light etc.) of the circuit. this paper shows a non-trivial polymorphic combinational circuit (5 bit majority/Boolean symmetry) which was designed at the gate level and then simulated using polymorphic NAND/NOR gates controlled by Vdd and some conventional gates at the transistor level. PSpice simulations have shown correct behavior of this circuit.
Technology forecasts predict that nanometer IC technologies will not yield large chip areas without non-functional transistors. Mechanism of redundancy and re-organization for self-repair at the transistor and gate le...
详细信息
ISBN:
(纸本)1424401844
Technology forecasts predict that nanometer IC technologies will not yield large chip areas without non-functional transistors. Mechanism of redundancy and re-organization for self-repair at the transistor and gate level are required, which can effectively handle realistic fault effects in CMOS logic circuits.
Field programmable gate arrays (FPGAs) provide a fast and flexible hardware for embedded control systems and signal processing. Despite this, tracing and monitoring of internal signals is awkward. FPGA vendors provide...
详细信息
ISBN:
(纸本)1424401844
Field programmable gate arrays (FPGAs) provide a fast and flexible hardware for embedded control systems and signal processing. Despite this, tracing and monitoring of internal signals is awkward. FPGA vendors provide their own tools to solve the debugging problems but they are not sufficient for real time monitoring. Instead, these signal tracing tools are good especially for tracing timing issues. this paper presents a method to monitor the internal signals of FPGA circuits by using an embedded microprocessor. the efficiency of this method is demonstrated with an FPGA-based active magnetic bearing control hardware.
One-to-All Broadcast (OAB) and All-to-All Broadcast (AAB) [5] group communications are frequently used in many parallel algorithms and if their overhead is excessive, performance degrades rapidly with processor count....
详细信息
ISBN:
(纸本)1424401844
One-to-All Broadcast (OAB) and All-to-All Broadcast (AAB) [5] group communications are frequently used in many parallel algorithms and if their overhead is excessive, performance degrades rapidly with processor count. this paper deals withthe design of a new application specific Bayesian Optimization Algorithm (BOA) and Standard Genetic Algorithm (SGA) that both produce almost optimal communication schedules for an arbitrary multiprocessor topology. We demonstrated the optimization process on hypercube and AMP topology [1] using Wormhole (WH) switching.
Systolic array architectures for approximate string matching play a significant role as hardware accelerators in biological applications. However, their wider use is limited by the lack of flexibility required by ofte...
详细信息
ISBN:
(纸本)1424401844
Systolic array architectures for approximate string matching play a significant role as hardware accelerators in biological applications. However, their wider use is limited by the lack of flexibility required by often variable tasks. In this respect, it is desirable to develop a procedure for automatic design and implementation of such accelerators to reach high performance and efficiency with as little human effort on the side of the designer as possible. this paper proposes the essential element of such procedure, a method for the calculation of generic systolic array parameters with respect to maximal performance and efficient resource utilization.
暂无评论