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检索条件"任意字段=9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems"
153 条 记 录,以下是1-10 订阅
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Test considerations about the structured ASIC paradigm
Test considerations about the structured ASIC paradigm
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9th ieee workshop on design and diagnostics of electronic circuits and systems
作者: Bernardi, P. Grosso, M. Politecn Torino Dipartimento Automat & Informat Cso Duca Abruzzi 24 I-10129 Turin Italy
We present a survey on the academic and industrial structured ASIC practices, especially focusing on the test strategies currently in use. then, we compare two possible test generation flows, underlining the most crit... 详细信息
来源: 评论
Architecture design for the Context Formatter in the H.264/AVC Encoder
Architecture Design for the Context Formatter in the H.264/A...
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9th ieee workshop on design and diagnostics of electronic circuits and systems
作者: Pastuszak, Grzegorz Warsaw Univ Technol Inst Radioelect Warsaw Poland
Hardware accelerators for H.264/AVC using arithmetic coding require special approaches to achieve high throughputs. this paper proposes an efficient architecture for the context formatter that is a part of the H.264/A... 详细信息
来源: 评论
design of a scalable asynchronous dataflow processor
Design of a scalable asynchronous dataflow processor
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9th ieee workshop on design and diagnostics of electronic circuits and systems
作者: Lampinen, Harri Perala, Pauli Vainio, Olli Tampere Univ Technol Inst Digital & Comp Syst POB 553 FIN-33101 Tampere Finland
this paper presents a scalable asynchronous dataflow processor. the main idea of the presented processor architecture is that the processing elements (PEs) are intelligent and can communicate directly with each other.... 详细信息
来源: 评论
A leakage-based random bit generator with on-line fault detection
A leakage-based random bit generator with on-line fault dete...
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9th ieee workshop on design and diagnostics of electronic circuits and systems
作者: Bucci, Marco Luzzi, Raimondo Infineon Technologies AG Germany
this paper presents a new, patent pending, random bit generator whose noise source exploits the leakage current in a reverse biased p-n junction. the circuit is described and a model is provided to estimate data-rate ... 详细信息
来源: 评论
How to improve a set of design validation data by using mutation-based test
How to improve a set of design validation data by using muta...
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9th ieee workshop on design and diagnostics of electronic circuits and systems
作者: Serrestou, Youssef Beroulle, Vincent Robach, Chantal LCIS INPG 50Rue Barthelemy Laffemas F-26902 Valence France
In current hardware design flow, functional verification is widely acknowledged as the crucial step. this paper presents a new contribution to reduce the cost of this step by automating it. We address here, one of the... 详细信息
来源: 评论
Run-time debugging and monitoring of FPGA circuits using embedded microprocessor
Run-time debugging and monitoring of FPGA circuits using emb...
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9th ieee workshop on design and diagnostics of electronic circuits and systems
作者: Penttinen, Aki Jastrzebski, Rafal Pollanen, Riku Pyrhonen, Olli Lappeenranta Univ Technol Dept Elect Engn Lappeenranta Finland
Field programmable gate arrays (FPGAs) provide a fast and flexible hardware for embedded control systems and signal processing. Despite this, tracing and monitoring of internal signals is awkward. FPGA vendors provide... 详细信息
来源: 评论
Evolutionary design of OAB and AAB communication schedules for networking systems on chips
Evolutionary design of OAB and AAB communication schedules f...
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9th ieee workshop on design and diagnostics of electronic circuits and systems
作者: Jaros, Jiri Dvorak, Vaclav Brno Univ Technol Fac Informat Technol Bozetechova 2 CZ-61266 Brno Czech Republic
One-to-All Broadcast (OAB) and All-to-All Broadcast (AAB) [5] group communications are frequently used in many parallel algorithms and if their overhead is excessive, performance degrades rapidly with processor count.... 详细信息
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Novel logic circuits controlled by Vdd
Novel logic circuits controlled by Vdd
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9th ieee workshop on design and diagnostics of electronic circuits and systems
作者: Sekanina, Lukas Starecek, Lukas Kotasek, Zdenek Brno Univ Technol Bozetechova 2 Brno Czech Republic
Polymorphic gates exhibit one or more additional functions in addition to the "main" function of the gate. the additional functions can be activated under certain conditions by changing control parameters (s... 详细信息
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Embedded self repair by transistor and gate level reconfiguration
Embedded self repair by transistor and gate level reconfigur...
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9th ieee workshop on design and diagnostics of electronic circuits and systems
作者: Kothe, Rene Vierhaus, Heinrich T. Coym, Torsten Verineiren, Wolfgang Straube, Bernd Brandenburg Tech Univ Cottbus POB 10 13 44 D-03013 Cottbus Germany Fraunhofer Inst Integrierte Schaltungen Branch Lab Design Automat Dresden Germany
Technology forecasts predict that nanometer IC technologies will not yield large chip areas without non-functional transistors. Mechanism of redundancy and re-organization for self-repair at the transistor and gate le... 详细信息
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Normal basis multipliers of general digit width applicable in ECC
Normal basis multipliers of general digit width applicable i...
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9th ieee workshop on design and diagnostics of electronic circuits and systems
作者: Novotny, Martin Schmidt, Jan CTU FEE Prague Dept Comp Sci & Engn Karlovo Nam 13Praha 2 Prague 12135 Czech Republic
We present two architectures of digit-serial normal basis multiplier over GF(29;9;9;). the multipliers were derived from the multiplier of Agnew et al. Proposed multipliers are scalable by the digit width of ... 详细信息
来源: 评论