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检索条件"任意字段=9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems"

共 153 条记录，以下是1-10 订阅

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Sports Activity Recognition with Deep Learning Models and Accelerometers 9

Sports Activity Recognition with Deep Learning Models and Ac...

引用

9th International Conference on Integrated circuits, design, and Verification, ICDV 2024

作者： Vu, Hoang-Dieu Pham, Quang-Tu Tran, Duc-Nghia Le, Hoang-Nam Pham, Dinh-Dat Nguyen, Van-Toi Dao, To-Hieu Tran, Duc-Tan Faculty of Electrical and Electronic Engineering Phenikaa University Yen Nghia Hanoi12116 Viet Nam Institute of Information Technology Vietnam Academy of Science and Technology Hanoi Viet Nam AandA Green Phoenix Group JSC No.167 Hoang NganTrung Hoa Cau Giay Hanoi11313 Viet Nam Graduate University of Sciences and Technology Vietnam Academy of Science and Technology Hanoi Viet Nam

ISBN: (纸本)9798350371864

Sport activity classification has become increasingly vital in various domains, including scientific research and healthcare. Accurate classification of Sports activities holds significant implications for behavior analysis and medical diagnostics. this paper investigates the classification of Sports activities using deep learning models such as Multilayer Perceptron (MLP), Convolutional Neural Networks (CNN), and Long Short-Term Memory (LSTM) networks applied to accelerometer sensor data. the accelerometer data is collected from a wearable device affixed to the waist of individuals engaged in daily activities. the performance of the deep learning models is evaluated by training them for 100 epochs and assessing their accuracy and confusion matrices on a validation dataset. the primary aim of this research is to compare the effectiveness of different deep learning models in accurately classifying Sports activities based on accelerometer data. © 2024 ieee.

关键词： Convolutional neural networks

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Method of Acoustic Emission Control of Multilayer Printed Circuit Boards of electronic Devices

Method of Acoustic Emission Control of Multilayer Printed Ci...

引用

Annual Siberian Russian workshop on Electron Devices and Materials (EDM)

作者： Saygid U. Uvaysov Viktoria V. Chernoverskaya Luu Ngoc Tien Nikita I. Prosvetov Ilya A. Ivanov Vo the Hai Department of Design and Production of Radioelectronic Devices MIREA - Russian Technological University Moscow Russia

ISBN: (数字)9798350389234

ISBN: (纸本)9798350353051

the article presents a method for controlling defects in the layering of multilayer printed circuit boards based on the use of acoustic emission and the study of the propagation of acoustic signals in the sample under study. It is shown that the proposed method, combining modeling, physical experiment and machine learning technologies in data processing, can become an effective tool for express control of multilayer printed circuit boards at the stage of their production. the article presents the structure of the method with a functional description of individual modules and blocks, shows the connection between computational and physical experiments, and the software used. the article also reflects the results of a study to assess the influence of the structure and number of layers of a multilayer board on the duration of a model experiment. In addition, the results of a study to determine the permissible range of variation in the characteristics of acoustic emission signals for a serviceable sample of a printed circuit board are presented, which made it possible to take into account in the model experiment the spread of parameters of printed circuit board materials and technological processes of their production. the research results presented in the article can be useful for design engineers, designers involved in the development of components and modules of radio electronic devices, specialists in the field of control and diagnostics of technical systems, students and postgraduates engaged in research in this field.

关键词： Manufacturing processes Computational modeling Printed circuits Production Acoustic emission Nonhomogeneous media Software

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A New Method for Path Criticality Calculation 19

A New Method for Path Criticality Calculation

引用

ieee 19th International Symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Tamasi, Robert Siebert, Miroslav Gramatova, Elena Fiser, Petr Slovak Univ Technol Bratislava Fac Informat & Informat Technol Ilkovicova 2 Bratislava 84216 Slovakia Czech Tech Univ Fac Informat Technol Thakurova 9 Prague 16000 6 Czech Republic

ISBN: (纸本)9781509024674

Technology scaling and manufacturing process affect the performance of digital circuits, making them more vulnerable to environmental influences. Some defects are manifested as delay faults. Some various factors have impact to signal propagation delay. A new method is presented for determining factors impact measurement on the path delay in the digital circuits. the method is focused to find the best weights of the factors used as parameters for the PaCGen (Parameterized Critical Path Generator) system. PaCGen is used for critical paths selection based on static timing analysis data with impact of factors to propagation delay. Experimental results are provided using the ISCAS'89 benchmark circuits.

关键词： delay fault testing path delay fault critical paths criticallity calculation

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Parity Waterfall Method 19

Parity Waterfall Method

引用

ieee 19th International Symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Borecky, Jaroslav Kohlik, Martin Kubatova, Hana Czech Tech Univ Dept Digital Design Fac Informat Technol Tech 9 Prague Czech Republic

ISBN: (纸本)9781509024674

this paper proposes a method for improvement of the fault-coverage capabilities of Field Programmable Gate Array (FPGA) designs. It utilizes Concurrent Error Detection (CED) techniques and the basic architectures of actual modern FPGAs the Look-Up Table (LUT) with two outputs. Proposed Parity Waterfall method is based on a cascade (waterfall) of several waves of inner parity generating the final parity of outputs of the whole circuit. the utilization of the (mostly) unused output of a two-output LUT allows the proposed method to cover any single possible routing or LUT fault with a small area overhead. the method is experimentally evaluated using the standard set of IWLS2005 benchmarks and using our simulator/emulator. the experimental results of the proposed parity waterfall method are compared with a similar existing technique (duplication with comparison). these results show that the area overhead is smaller than the overhead of the duplication with comparison method for all of the tested circuits and 100% fault coverage is achieved.

关键词： Field programmable gate arrays (FPGA)

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Proposal and Properties of Ring Oscillator-Based PUF on FPGA

Proposal and Properties of Ring Oscillator-Based PUF on FPGA

引用

18th ieee International Symposium on design and diagnostics of electronic circuits and systems (DDECS 2015)

作者： Kodytek, Filip Lorencz, Robert Czech Tech Univ Dept Comp Syst Thakurova 9 Prague 16000 Czech Republic

this paper deals with design of physical unclonable functions (PUFs) based on field-programmable gate array (FPGA). the goal was to propose a cheap, efficient and secure device identification or even a cryptographic key generation based on PUFs. therefore, a design of a ring oscillator (RO)-based PUF producing more output bits from each RO pair is presented. 24 Digilent Basys 2 FPGA boards (Spartan-3E) and 6 Digilent Nexys 3 FPGA boards (Spartan-6) were tested and statistically evaluated indicating suitability of the proposed design for device identification. A stable PUF output is required for generating cryptographic keys. As post-processing technique to further improve the efficiency of this PUF design, we used Gray code on the obtained bits from RO pairs. Ultimately, the PUF design is combined with error correction code and together with Gray code is able to generate cryptographic keys of sufficient length.

关键词： PUF FPGA ring oscillator key generation error correction code

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design of a Novel 170GHz-260GHz Sub-harmonic Mixer Based on Planar Schottky Diodes

Design of a Novel 170GHz-260GHz Sub-harmonic Mixer Based on ...

引用

ieee UK-Europe-China workshop on Millimeter Waves and thz Technologies

作者： Zhuo Chen Jianqin Deng Mo Wang Jinxian Liu Wanshun Jiang Science and Technology on Electronic Test & Measurement Laboratory The 41st Institute of CETC

ISBN: (纸本)9781509022779

A novel 170GHz-260GHz sub-harmonic mixer (SHM) is designed and analyzed in this paper. the simulation results and measurement results is compared. the mixer is based on a low parasitic anti-parallel pair of GaAs planar Schottky diodes. the circuits are integrated with the high pass filter and IF filter, which are fabricated on a suspended quartz-based substrate. the best conversion loss of mixer is 7dB with 6dBm LO power. Within the band of 170GHz-260GHz, the mixer's conversion loss is below 13dB.

关键词： GaAs planar Schottky diodes Sub-harmonic mixer Conversion loss

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A design of ring oscillator based PUF on FPGA 18

A design of ring oscillator based PUF on FPGA

引用

ieee 18th International Symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Kodytek, Filip Lorenez, Robert Czech Tech Univ Dept Comp Syst Thakurova 9 Prague Czech Republic

ISBN: (纸本)9781479967803

this paper deals with design of Physical Unclonable Functions (PUFs) based on FPGA. the goal was to propose a cheap, efficient and secure device identification or even a cryptographic key generation based on PUFs. therefore, a proposal of a ring oscillator (RO) based PUF producing more output bits from one RO pair is presented. 24 Digilent Basys 2 FPGA boards were tested and statistically evaluated indicating suitability of the proposed design for device identification.

关键词： PUF FPGA ring oscillator

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High throughput floating-point dividers implemented in FPGA 18

High throughput floating-point dividers implemented in FPGA

引用

ieee 18th International Symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Malik, Peter Slovak Acad Sci Inst Informat Dubravska Cesta 9 Bratislava 84507 Slovakia

ISBN: (纸本)9781479967803

New high throughput floating-point dividers implemented in FPGA based on different fast computation division algorithms are proposed. the hardware implementations uses 32-bit floating-point single precision. the implementations include both multiplicative inverse and division. the proposed hardware implementations are designed with high computation speed and throughput. they are oriented for high computation demanding applications with multiple division computations in short sequences.

关键词： dedicated hardware divider floating-point FPGA HPC ieee 754

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the design of a Ka-band Planar Broadband slot-coupled Antenna

The Design of a Ka-band Planar Broadband slot-coupled Antenn...

引用

2016 ieee 9th UK-Europe-China workshop on Millimetre Waves and Terahertz Technologies

作者： Yuan Song Bo Zhang Yong Fan EHF Key Laboratory of Fundamental Science University of Electronic Science and Technology of China Chengdu National Key Laboratory of Application Specific Integrated Circuits Hebei Semiconductor Research Institute IEEE

In this paper,a kind of Ka-band Planar broadband slot-coupled antenna is *** order to broaden the bandwidth,use E-shaped patch on the basis of the copper axial feed *** two parallel slots is equivalent to two LC resonant circuits which has coupling ***,slot on the ground through the simulation,the center frequency of the antenna is 29 GHZ and its relative bandwidth is improved up to twice as much.

关键词： wide-band antenna slotting Ka-band

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the design of 850GHz Subharmonic Mixer Based on Schottky Diodes

The design of 850GHz Subharmonic Mixer Based on Schottky Dio...

引用

2016 ieee 9th UK-Europe-China workshop on Millimetre Waves and Terahertz Technologies

作者： Zhongqian Niu Bo Zhang Yong Fan Li Sen Zhang Dong Xing Jun Long Wang EHF Key Laboratory of Fundamental Science University of Electronic Science and Technology of China National Key Laboratory of Application Specific Integrated Circuit Hebei Semiconductor Research Institute IEEE

this paper presents the design and simulation investigation of a 850 GHz low-loss subharmonical mixer based on GaAs Schottky barrier *** group analyzed the topology of subharmonic mixer,device modeling of Schottky diodes,the 3D electromagnetic passive circuits and the mixer circuitry with optimum *** antiparallel diodes pair is fabricated from China electronics Technology Group Coporation-13 Institute,flip-chip mounted on a 25um-thick gallium-arsenide substrate.

关键词： Terahertz Schottky diodes subharmonic mixer flip-chip

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