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检索条件"任意字段=9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems"

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design and Simulation of Runtime Reconfigurable systems

Design and Simulation of Runtime Reconfigurable Systems

引用

11th International workshop on design and diagnostics of electronic circuits and systems (DDECS)

作者： thilo Pionteck Carsten Albrecht Roman Koch Torben Brix Erik Maehle Institute of Computer Engineering University of Lübeck Lubeck Germany

this paper presents an architectural framework and simulation model for tile-based runtime reconfigurable systems. the framework accounts for all hardware limitations of actual FPGA devices and is based on the division of the reconfigurable system partition into a set of small tiles. these tiles can either be exchanged individually at runtime or can be grouped to larger tiles and be exchanged as a whole. the adaptive tile size allows the realization of hardware modules of varying sizes. For easing the system design process a SystemC simulation methodology at a high abstraction level is presented which provides support for all architectural features of the hardware framework. In particular, the capability of simulating runtime reconfigurable systems is supported by the simulation methodology without modifying the SystemC kernel. the applicability of the architectural framework and of the simulation model is demonstrated by means of an example.

关键词： Hardware Field programmable gate arrays Tiles Computational modeling Computer simulation Runtime Kernel Logic devices Reconfigurable logic Libraries

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Process Tolerant design Using thermal and Power-Supply Tolerance in Pipeline Based circuits

Process Tolerant Design Using Thermal and Power-Supply Toler...

引用

11th International workshop on design and diagnostics of electronic circuits and systems (DDECS)

作者： J. Semiao J. J. Rodriguez-Andina F. Vargas M. Santos I. Teixeira P. Teixeira University of Algarve Portugal University of Vigo Spain PUCRS Brazil IST/INESC Portugal

this paper describes a thermal and power-supply tolerant design methodology for pipeline based circuits. It is shown that by making the circuit more tolerant to V{sub}(DD) and temperature (T) instability, even in the presence of process variations, a yield loss reduction is achieved. the goal is to improve signal integrity in the presence of power-supply voltage (VDD) and/or temperature (T) variations, without degrading circuit performance. By using time borrowing techniques, data integrity loss is avoided, and circuit tolerance to VDD and/or temperature variations is enhanced. the methodology is based on a Dynamic Delay Buffer (DDB) block, used to sense VDD/T variations and to induce dynamic clock skews driving a limited subset of key memory elements. Monte Carlo simulations are used to demonstrate that the proposed methodology still holds, even in the presence of process variations.

关键词： Process design Pipelines Circuit testing Clocks Delay Degradation Temperature Timing Performance analysis Algorithm design and analysis

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Web-Based Framework for Parallel Distributed Test

Web-Based Framework for Parallel Distributed Test

引用

11th International workshop on design and diagnostics of electronic circuits and systems (DDECS)

作者： Eero Ivask Jaan Raik Raimund Ubar Tallinn University of Technology Tallinn Estonia

In this paper we describe web-based distributed system suitable for acceleration of fault simulation in digital circuits. Framework has three-tier client server concept. Java applets are used for user interfaces. Java servlet on master server supports communication, task partitioning, user tracking, data management, etc. HTTP protocol based solution is used, since it is well established and flexible in firewall-protected environments. Reuse of existing test tools by encapsulation into Java agents extends the lifecycle and value of these tools. Considerable fault simulation speedup was gained in experiments. Two types of fault set partitioning were tried: adjacent fault selection and random fault selection. the latter is able to ensure more equal execution times for subtasks and therefore contributes to overall shorter parallel simulation time.

关键词： Circuit faults Java Circuit testing Web server Acceleration Circuit simulation Digital circuits User interfaces Protocols Protection

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A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations

A Resistorless Voltage Reference Source for 90 nm CMOS Techn...

引用

11th International workshop on design and diagnostics of electronic circuits and systems (DDECS)

作者： Tomasz Borejko Witold A. Pleskacz Institute of Microelectronics & Optoelectronics Warsaw University of Technology Warsaw Poland

A new compact low power voltage reference source for wireless and embedded applications is described. the reference voltage source has been designed in a mixed-signal UMC 90 nm CMOS process using subthreshold characteristics for generating a constant voltage of 423 mV at supply voltages from 1.1 V to 3.3 V with total current consumption 270 nA. the proposed circuit occupies 0.001 mm{sup}2 chip area and achieves less than 110 ppm/℃ for all process corners and temperature variation from -40℃ to 125℃. the power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz is lower than -50 dB and -30 dB, respectively. the equivalent output voltage noise in the bandwidth from 1 Hz to 10 MHz reaches 218 μV{sub}(RMS).

关键词： CMOS technology CMOS process Temperature sensors Low voltage Wireless sensor networks Character generation circuits Power supplies Filtering Capacitors

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Calculation of LFSR Seed and Polynomial Pair for BIST Applications

Calculation of LFSR Seed and Polynomial Pair for BIST Applic...

引用

11th International workshop on design and diagnostics of electronic circuits and systems (DDECS)

作者： A. Jutman A. Tsertov R. Ubar Tallinn University of Technology Tallinn Estonia

Polynomial selection for LFSR-based BIST schemes has been typically left out of the scope of active research in the recent works due to lack of analytical methods that address this issue. Usage of primitive polynomial with a small number of feedbacks is considered a classical rule of thumb that is usually implemented. Although being beneficial for very long test sequences, primitive polynomial cannot guarantee fast fault coverage growth, which is a critical issue in pseudo-random-pattern-generator-based embedded test approaches. Hence, selecting a good initial state would be the main instrument for getting the fast coverage gain. In this work, we propose a formal analytical method to calculate a customized polynomial and seed pair for each separate design/test case. this novel technique allows shortening BIST runtimes and increasing fault coverage by embedding given efficient test patterns into the LFSR sequence. Being used in mixed-mode BIST techniques, the method shows decreasing trend in test application time and/or necessary test pattern storage resources. Our comparison against primitive polynomial based sequences support these observations.

关键词： Polynomials Built-in self-test Circuit testing Circuit faults Automatic test pattern generation Automatic testing electronic equipment testing System testing Runtime Semiconductor device manufacture

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Redundancy and test-pattern generation for asynchronous quasi-delay-insensitive combinational circuits

Redundancy and test-pattern generation for asynchronous quas...

引用

10th ieee International workshop on design and diagnostics of electronic circuits and systems

作者： Efthymiou, Aristides Univ Edinburgh Sch Informat Edinburgh EH9 3JZ Midlothian Scotland

ISBN: (纸本)9781424411610

Most of the early work on testing asynchronous combinational circuits ignored faults inside C elements, a common building block in these circuits. Using a standard cell based design, where C elements are built using majority gates, we show that a number of faults are un-testable in some implementations, while others are undetected by previously proposed tests, which yield a fault coverage of only 70-80% even in the small circuits examined here. We present a novel test pattern generation algorithm based on the D algorithm and time-frame expansion that can automatically detect all testable stuck-at faults in these families of combinational asynchronous circuits. Finally we present a comparison of the test pattern lengths achieved by this method with previously published full-scan based methods.

关键词： Timing circuits

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Decomposition of logic functions in Reed-Muller spectral domain

Decomposition of logic functions in Reed-Muller spectral dom...

引用

10th ieee International workshop on design and diagnostics of electronic circuits and systems

作者： Hrynkiewicz, Edward Kolodzinski, Stefan Silesian Tech Univ Inst Elect Gliwice Poland

ISBN: (纸本)9781424411610

the paper deals with the problems of logic function decomposition in Reed-Muller spectral domain. the Ashenhurst and the Curtis decompositions are considered. the decompositions are executed on Positive Polarization Reed-Muller spectrum of decomposed functions. the elaborated methods of decomposition are guided to implementation of logic functions in LUT based FPGA. the results are very promising.

关键词： Computer circuits

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Open defects caused by scratches and yield modelling in deep sub-micron integrated circuit

Open defects caused by scratches and yield modelling in deep...

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10th ieee International workshop on design and diagnostics of electronic circuits and systems

作者： Jonca, Wlodzimierz Warsaw Univ Technol Inst Microelect & Optoelect PL-00661 Warsaw Poland

this paper(1) tries to find out whether commonly used spot defect fault model is still viable for Deep Sub-Micron (DSM) integrated circuits9; test and yield model. It is believed that for DSM products spot defects ... 详细信息

ISBN: (纸本)9781424411610

this paper(1) tries to find out whether commonly used spot defect fault model is still viable for Deep Sub-Micron (DSM) integrated circuits' test and yield model. It is believed that for DSM products spot defects may be no longer major source of yield loss. Results from number of computer experiments are presented and discussed.

关键词： Integrated circuits

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Establishing a new course in reconfigurable logic system design

Establishing a new course in reconfigurable logic system des...

引用

10th ieee International workshop on design and diagnostics of electronic circuits and systems

作者： Torresen, Jim Norendal, Jorgen Glette, Kyrre Univ Oslo Dept Informat POB 1080 N-0316 Oslo Norway

ISBN: (纸本)9781424411610

Reconfigurable computing has grown to become important in hardware design. In autumn 2005, we taught for the first time a new course in digital system design with its main focus on FPGA technology and design using VHDL. this paper reports about the various issues dealt with including what topics to cover, text book selection, lab exercises etc. A summary of the students feedback is also included.

关键词： systems analysis

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ESD failures of integrated circuits and their diagnostics using transmission line pulsing

ESD failures of integrated circuits and their diagnostics us...

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10th ieee International workshop on design and diagnostics of electronic circuits and systems

作者： Piatek, Z. Kolodziejski, J. F. Pleskacz, W. A. Warsaw Univ Technol PL-00661 Warsaw Poland Inst Elect Technol Warsaw Poland

ISBN: (纸本)9781424411610

In the work typical ESD failures of integrated circuits and ESD testing methods are presented. Authors describe dependencies between ESD models and different ESD failures. In order to allow more advanced ESD testing of integrated circuits, Transmission Line Pulsing is proposed and its correlation to HBM method described. Finally conclusions based on up-to-date research and test results obtained with the help of the assembled TLP tester are provided.

关键词： Integrated circuits

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