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共 153 条记录，以下是101-110 订阅

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design and analysis of a new self-testing adder which utilizes polymorphic gates

Design and analysis of a new self-testing adder which utiliz...

引用

10th ieee International workshop on design and diagnostics of electronic circuits and systems

作者： Sekanina, Lukas Brno Univ Technol Fac Informat Technol Brno 61266 Czech Republic

ISBN: (纸本)9781424411610

this paper describes a new self-testing 1-bit full adder. this circuit consists of three polymorphic NAND/NOR gates, two XOR gates and two inverters. the adder is able to detect a reasonable number of stuck-at-faults without the need of any additional logic and diagnostic signals. A fault is indicated by oscillations at the carry-out output. Properties of n-bit carry-propagate adder which is composed of the proposed 1-bit self-testing adders are investigated.

关键词： Adders

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Flip-flops and scan-path elements for nanoelectronics

Flip-flops and scan-path elements for nanoelectronics

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10th ieee International workshop on design and diagnostics of electronic circuits and systems

作者： Kothe, R. Vierhaus, H. T. Brandenburg Tech Univ Cottbus Inst Comp Sci POB 10 13 44 D-03013 Cottbus Germany

ISBN: (纸本)9781424411610

Fault tolerant design has recently gained new attention due to the increasing volatility of nano-electronic circuits from transient fault effects. Latches and flip-flops are the potential sources of errors. Novel designs of fault-tolerant flip-flops encompass multiple latches, which can also be used to accommodate the double-latched scan for dynamic test. the resulting scan-path elements are fault-tolerant for functional operation and static scan test.

关键词： Flip flop circuits

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Built in defect prognosis for embedded memories

Built in defect prognosis for embedded memories

引用

10th ieee International workshop on design and diagnostics of electronic circuits and systems

作者： Dubey, Prashant Garg, Akhil Bhaskarani, Sravan Kumar STMicroelect India Pvt Ltd Plot 1Knowledge Pk 3 Greater Noida India

ISBN: (纸本)9781424411610

With the shrinking technology and increasing statistical defects, multiple design respins are required based on yield learning. Hence, a solution is required to efficiently diagnose the failure types of memory during production in the shortest time frame possible. this paper introduces a novel method of fault classification through image based prognosis of predefined fail signature dictionary. In contrary to the existing Bitmap Diagnosis methodologies, this method predicts the compressed failure map without generating and transferring complete Bitmap to the tester. the proposed methodology supports testing through a very low cost ATE. this architecture is partitioned to achieve sharing among various memories and at-speed testing.

关键词： memory test diagnostics bitmap yield learning

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A novel parity bit scheme for SBox in AES circuits

A novel parity bit scheme for SBox in AES circuits

引用

10th ieee International workshop on design and diagnostics of electronic circuits and systems

作者： Di Natale, G. Flottes, M. L. Rouzeyre, B. Univ Montpellier 2 CNRS UMR 5506 Lab Informat Robot & Microelect Montpellier 161 Rue Ada F-34392 Montpellier 5 France

ISBN: (纸本)9781424411610

this paper addresses an efficient concurrent fault detection scheme for the SBox hardware implementation of the AES algorithm. Concurrent fault detection is important not only to protect the encryption/decryption process from random and production faults. It will also protect the system against side-channel attacks, in particular fault-based attacks, i.e. the injection of faults in order to retrieve the secret key. We will prove that our solution is very effective while keeping the area overhead very low.

关键词： Fault detection

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Two-level logic synthesis for low power based on new model of power dissipation

Two-level logic synthesis for low power based on new model o...

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10th ieee International workshop on design and diagnostics of electronic circuits and systems

作者： Brzozowski, I. Kos, A. AGH Univ Sci & Technol Al Mickiewicza 30 PL-30059 Krakow Poland

ISBN: (纸本)9781424411610

Accurate analysis of CMOS gate power dissipation shows that amount of consumed energy depends on a reason of the gate switching. Number of activated inputs and type of applied signals have an influence on dynamic power dissipation of the gate due to dynamic reconfiguration of internal gate parasitic capacitors. therefore, authors propose new modeling of dynamic power dissipation in static CMOS gates. Accurate modeling of dynamic power dissipation needs to take into consideration changes of all input signals. So, authors introduce new measure of digital circuit activity - gate driving way - for precise modeling of power dissipation. Based on conclusions flowing from the model analysis, authors propose method for two-level low-power circuits design.

关键词： CMOS integrated circuits

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design issues of a low frequency low-pass filter for medical applications using CMOS technology

Design issues of a low frequency low-pass filter for medical...

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10th ieee International workshop on design and diagnostics of electronic circuits and systems

作者： Timar, Andras Rencz, Marta Budapest Univ Technol & Econ Dept Electron Devices 3 Goldmann Gyorgy Sq Budapest Hungary

ISBN: (纸本)9781424411610

In the past few decades, medical and biological researches gained more and more attention. the ever-growing need for such researches caused many medical applications to develop. Collecting data from a living human body is a complex task and needs circumspection. In this paper, specific issues of the most important part of such a data acquisition system is presented, the design of a low pass filter. the major issue to overcome in the design of a system that is aimed at being built into the human body is creating large value capacitances needed to the realization of filters for the specific application. After presenting the special requirements for low pass filters for medical applications the method of creating large capacitors is presented in details in the paper.

关键词： Low pass filters

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Architecture for highly reliable embedded flash memories

Architecture for highly reliable embedded flash memories

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10th ieee International workshop on design and diagnostics of electronic circuits and systems

作者： Godard, Benoit Daga, Jean-Michel Torres, Lionel Sassatelli, Gilles ATMEL Embedded Non Volatile Memory Grp Libraries & Design Tools Dept F-13106 Rousset France Lab Informat Robot Montpellier France

ISBN: (纸本)9781424411610

Non-volatile embedded Flash (eFlash) memories are very popular in systems-on-a-Chip (SoC). these memories are based on the well-known floating gate concept. While densities and quality constraints are increasing, the reliability becomes a growing up issue. For eFlash memories, endurance and retention issues are at the root of reliability losses. To improve reliability, eFlash memories designs usually use techniques such as Error Correcting Codes (ECC), Redundancy and threshold Voltage (V-T) Analysis. In this paper, an implementation of these techniques is proposed through an architecture. thanks to eFlash specificity, the correction capacity is improved via a double correction scheme. Additionally, each time an operation is performed on a memory element, a smart reliability management tracks online errors and weak bits. When few issues in a word catch out the double error correction scheme, a Refresh and Repair with row redundancy process is engaged.

关键词： threshold voltage

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Analysis of noise margins due to device parameter variations in sub-100nm CMOS technology

Analysis of noise margins due to device parameter variations...

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10th ieee International workshop on design and diagnostics of electronic circuits and systems

作者： Liang, Zhicheng Ikeda, Makoto Asada, Kunihiro Univ Tokyo Dept Elect Engn Bunkyo Ku 7-3-1 Hongo Tokyo 1138656 Japan

ISBN: (纸本)9781424411610

Increasing level of process variation in the sub-100nm silicon technology is becoming an important issue. In this paper we describe an approach to estimate the impact of process variations on the static CMOS and the dual-rail PLA down to 32nm process. this approach is built on accurate variation modeling, published data including the ITRS, Predictive Technology Models, and Monte-Carlo analysis. the analysis results show that a challenge due to insufficient noise margins is posed to the static CMOS at 32nm, and to the dual-rail PLA from 90nm. then a one-side virtual ground structure is also proposed to improve the noise margins of the dual-rail PLA. the improved dual-rail PLA is shown to work down to 32nm process with keeping an operational margin of 150mv.

关键词： CMOS integrated circuits

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Automatic generation of circuits for approximate string matching

Automatic generation of circuits for approximate string matc...

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10th ieee International workshop on design and diagnostics of electronic circuits and systems

作者： Martinek, Tomas Fucik, Otto Beck, Patrik Lexa, Matej Brno Univ Technol Fac Informat Technol Bozetechova 2 Brno 61266 Czech Republic CESNET zspo Prague 160 Czech Republic Masaryk Univ Fac Informat Brno Czech Republic

ISBN: (纸本)9781424411610

Hardware accelerators for approximate string matching play an important role in an increasing number of modern bioinformatic applications. they are able to reduce the task complexity from quadratic to linear and show a speed up in orders of hundreds when compared with the respective software implementation. However, their wider use is limited by the lack of flexibility and modularity required by often variable tasks. In this respect, it is desirable to develop a procedure for automatic design and implementation of such accelerators' to reach high performance and efficiency typical for strongly optimized architectures, with as little human effort on the side of the designer as possible. this paper proposes the essential element of such a procedure, a method for the calculation of generic hardware architecture parameters. the proposed method is evaluated on a range of typical approximate string matching tasks. It demonstrates the differences in the designed architecture, when performance of individual tasks is maximized.

关键词： Timing circuits

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Cost-efficient synthesis for sequential circuits implemented using embedded memory blocks of FPGA's

Cost-efficient synthesis for sequential circuits implemented...

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10th ieee International workshop on design and diagnostics of electronic circuits and systems

作者： Borowik, Grzegorz Falkowski, Bogdan Luba, Tadeusz Warsaw Univ Technol Inst Telecommun Nowowiejska 15-19 PL-00665 Warsaw Poland

Modern FPLD devices have a very complex structure. they combine PLA-like structures as well as FPGA9;s and even memory-based structures. However, the lack of an appropriate synthesis method does not allow the featu... 详细信息

ISBN: (纸本)9781424411610

Modern FPLD devices have a very complex structure. they combine PLA-like structures as well as FPGA's and even memory-based structures. However, the lack of an appropriate synthesis method does not allow the features of the modern FPLD's to be fully exploited. In this paper, an important problem of state assignment for an FSM as an extension of the previous research on ROM-based FSM implementation is presented. We pinpoint the sources of additional optimization of the functional decomposition and relate them to the state encoding conditions. the method is based on a reduction of a state assignment problem to a graph coloring problem. To this end, the so called multi-graph of incompatibility of memory T-words is applied. As a result, a new design technique for implementation of sequential circuits using embedded memory blocks of FPGA's has been developed. Preliminary experimental results are extremely encouraging.

关键词： Field programmable gate arrays (FPGA)

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