Hardware accelerators for H.264/AVC using arithmetic coding require special approaches to achieve high throughputs. this paper proposes an efficient architecture for the context formatter that is a part of the H.264/A...
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ISBN:
(纸本)1424401844
Hardware accelerators for H.264/AVC using arithmetic coding require special approaches to achieve high throughputs. this paper proposes an efficient architecture for the context formatter that is a part of the H.264/AVC binary encoder. Five versions of the architecture are developed to match different throughputs. the implementation results show that the proposed versions of the context formatter match the performance of corresponding arithmetic coders.
In current hardware design flow, functional verification is widely acknowledged as the crucial step. this paper presents a new contribution to reduce the cost of this step by automating it. We address here, one of the...
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ISBN:
(纸本)1424401844
In current hardware design flow, functional verification is widely acknowledged as the crucial step. this paper presents a new contribution to reduce the cost of this step by automating it. We address here, one of the principal challenges of dynamic verification, by providing a new approach for automatic test generation. this approach combines mutation-based test techniques and genetic algorithms to produce stimuli for design under test. the feasibility of the proposed approach is assessed with a preliminary implementation, and some framework has been tested.
Polymorphic gates exhibit one or more additional functions in addition to the "main" function of the gate. the additional functions can be activated under certain conditions by changing control parameters (s...
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ISBN:
(纸本)1424401844
Polymorphic gates exhibit one or more additional functions in addition to the "main" function of the gate. the additional functions can be activated under certain conditions by changing control parameters (such as temperature, Vdd, light etc.) of the circuit. this paper shows a non-trivial polymorphic combinational circuit (5 bit majority/Boolean symmetry) which was designed at the gate level and then simulated using polymorphic NAND/NOR gates controlled by Vdd and some conventional gates at the transistor level. PSpice simulations have shown correct behavior of this circuit.
Technology forecasts predict that nanometer IC technologies will not yield large chip areas without non-functional transistors. Mechanism of redundancy and re-organization for self-repair at the transistor and gate le...
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ISBN:
(纸本)1424401844
Technology forecasts predict that nanometer IC technologies will not yield large chip areas without non-functional transistors. Mechanism of redundancy and re-organization for self-repair at the transistor and gate level are required, which can effectively handle realistic fault effects in CMOS logic circuits.
Field programmable gate arrays (FPGAs) provide a fast and flexible hardware for embedded control systems and signal processing. Despite this, tracing and monitoring of internal signals is awkward. FPGA vendors provide...
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ISBN:
(纸本)1424401844
Field programmable gate arrays (FPGAs) provide a fast and flexible hardware for embedded control systems and signal processing. Despite this, tracing and monitoring of internal signals is awkward. FPGA vendors provide their own tools to solve the debugging problems but they are not sufficient for real time monitoring. Instead, these signal tracing tools are good especially for tracing timing issues. this paper presents a method to monitor the internal signals of FPGA circuits by using an embedded microprocessor. the efficiency of this method is demonstrated with an FPGA-based active magnetic bearing control hardware.
One-to-All Broadcast (OAB) and All-to-All Broadcast (AAB) [5] group communications are frequently used in many parallel algorithms and if their overhead is excessive, performance degrades rapidly with processor count....
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ISBN:
(纸本)1424401844
One-to-All Broadcast (OAB) and All-to-All Broadcast (AAB) [5] group communications are frequently used in many parallel algorithms and if their overhead is excessive, performance degrades rapidly with processor count. this paper deals withthe design of a new application specific Bayesian Optimization Algorithm (BOA) and Standard Genetic Algorithm (SGA) that both produce almost optimal communication schedules for an arbitrary multiprocessor topology. We demonstrated the optimization process on hypercube and AMP topology [1] using Wormhole (WH) switching.
Systolic array architectures for approximate string matching play a significant role as hardware accelerators in biological applications. However, their wider use is limited by the lack of flexibility required by ofte...
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ISBN:
(纸本)1424401844
Systolic array architectures for approximate string matching play a significant role as hardware accelerators in biological applications. However, their wider use is limited by the lack of flexibility required by often variable tasks. In this respect, it is desirable to develop a procedure for automatic design and implementation of such accelerators to reach high performance and efficiency with as little human effort on the side of the designer as possible. this paper proposes the essential element of such procedure, a method for the calculation of generic systolic array parameters with respect to maximal performance and efficient resource utilization.
We present two architectures of digit-serial normal basis multiplier over GF(29;9;9;). the multipliers were derived from the multiplier of Agnew et al. Proposed multipliers are scalable by the digit width of ...
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ISBN:
(纸本)1424401844
We present two architectures of digit-serial normal basis multiplier over GF(2'''). the multipliers were derived from the multiplier of Agnew et al. Proposed multipliers are scalable by the digit width of general value in difference of the multiplier of Agnew et al. that may be scaled only by digit widththat divides the degree m. this helps designers to trade area for speed e.g. in pubhc-key cryptographic systems based on elliptic-curves, where m should be a prime number. Functionality of multipliers has been tested by simulation and implemented in Xilinx Virtex 4 FPGA.
this paper describes realization of a project that is concerned with a diagnostic system of a SOC. the diagnostic system used RESPIN architecture is based on the ieee 1500 standard and allows testing of cores by compr...
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ISBN:
(纸本)1424401844
this paper describes realization of a project that is concerned with a diagnostic system of a SOC. the diagnostic system used RESPIN architecture is based on the ieee 1500 standard and allows testing of cores by compressed test patterns. the patterns for certain core under test are decompressed in the scan chains of the other idle core during the test time. the compressed form of the test patterns is prepared by the algorithm COMPAS and stored in the memory of the SOC. the diagnostic system was implemented to the FPSLIC AT94K circuit that contain FPGA for cores, processor for control test procedure and the memory for storing the compressed test data in one system chip.
this paper introduces a Multiple Valued Counter, based on recharged semi floating gate structures. the counter starts at a sampled voltage, and counts from there, using an input clock signal as an input. Depending on ...
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ISBN:
(纸本)1424401844
this paper introduces a Multiple Valued Counter, based on recharged semi floating gate structures. the counter starts at a sampled voltage, and counts from there, using an input clock signal as an input. Depending on the sampled value and the phase of the input clock signal-the counter can count both up and down. the counting steps can be varied adjusting the input clock amplitude, which in combination with different output resetting values allows a set of different counting radixes. Recharged semi floating structures may suffer from an offset at the output due to mismatch in the inverter structures. this counter minimizes this problem with a build in offset cancellation, which is an advantage for non capacitive readouts.
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