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检索条件"任意字段=9th International Conference on Algorithms and Architectures for Parallel Processing"

共 2828 条记录，以下是111-120 订阅

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Simulation Study of Submarine Evading Anti-Submarine Helicopter Search Based on Improved Particle Swarm Optimization Algorithm

Simulation Study of Submarine Evading Anti-Submarine Helicop...

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6th international conference on Intelligent Computing and Signal processing (ICSP)

作者： Jiaming Zhang Jian Liu Navy Submarine Academy Qingdao China

ISBN: (数字)9798350376548

ISBN: (纸本)9798350376555

It is a typical path optimization problem for submarines to avoid dipping sonar and sonobuoy joint search in a certain sea area by pure maneuvering. Particle swarm optimization ( PSO ) and improved particle swarm optimization ( IPSO ) based on parallel computing are used to solve this problem by using nonlinear inertia weight and improved learning factor. the objective function adopts the principle of distance maximization and the principle of minimum and maximum respectively. the simulation results show that the parallel improved particle swarm optimization algorithm can quickly calculate and obtain a better feasible solution, and the submarine can meet the objective function through maneuver avoidance to meet the submarine defense needs.

关键词： Simulation Signal processing algorithms Sonar parallel processing Signal processing Linear programming Trajectory Particle swarm optimization Underwater vehicles Optimization

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NPB-PSTL: C++ STL algorithms with parallel Execution Policies in NAS parallel Benchmarks

NPB-PSTL: C++ STL Algorithms with Parallel Execution Policie...

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Euromicro conference on parallel, Distributed and Network-Based processing

作者： Júnior Löff Renato B. Hoffmann Arthur S. Bianchessi Leonardo Mallmann Dalvan Griebler Walter Binder Faculty of Informatics Università della Svizzera italiana (USI) Lugano Switzerland Pontifical Catholic University of Rio Grande do Sul (PUCRS) Porto Alegre Brazil

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

the C++ language continually evolves through formal specifications established by its standards committee, proposing new features to maintain $\mathrm{C}++$ as a relevant programming language while improving usability, performance, and portability across platforms. With the addition of parallel Standard Template Library (STL) algorithms in C++17, programmers can now leverage parallel processing capabilities via vendor-neutral parallel execution policies. this study presents an adaptation of the NAS parallel Benchmarks (NPB)—a well-established suite of applications for evaluating parallel architectures-by porting its sequential C-style code to use C++ STL abstractions and performance-portable parallelism features. Our goals are to (1) assess the suitability of C++ STL for scientific applications like the ones in the NPB and (2) provide a comparative performance and portability of STL algorithms’ parallel execution policies across different multicore architectures (x86 and AArch64). Results indicate that the performance of parallel STL algorithms is often close to that of optimized handwritten versions (OpenMP, Intel TBB, and FastFlow) on different architectures, with notable shortfalls. Across all NPB benchmarks, the STL algorithms’ geometric mean shows sequential execution times that are between 3.76% and $\mathrm{6. 9 \%}$ higher, while parallel executions may reach a geometric mean of up to $\mathrm{2 1. 2 1 \%}$ higher execution time.

关键词： parallel programming Multicore processing Software algorithms C++ languages Benchmark testing parallel processing Data structures Libraries Hardware Standards

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Research on Intelligent Prediction of Blasting Vibration Based on parallel SVM in Big Data Environment 24

Research on Intelligent Prediction of Blasting Vibration Bas...

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9th international conference on Intelligent Information processing, ICIIP 2024

作者： Wang, Hui Rao, Xiaokang Li, Chunhui WUHAN CITY POLYTECHNIC China Wuhan University China Rajamangala University of Technology Tawan-Ok Thailand

ISBN: (纸本)9798400718076

Blasting vibration is one of the main negative effects of blasting construction. It is influenced by many external factors and has a complex nonlinear relationship with them. How to predict and reduce the blasting vibration effect while completing the blasting construction is a long-term concern in the blasting industry. With the development of the Internet of things and mobile devices, various types of data collection in blasting projects have become quick and varied. Many massive, multi-source, heterogeneous blasting vibrations, and geological data have been gathered. Such a large-scale data set implies potentially useful information and presents significant challenge relevant to traditional computation theories and methods as well. Based on the massive data related to blasting vibration, this paper uses Hadoop to establish a distributed computing framework, establishes a big data analysis platform to carry out massive data mining and analysis, and builds a parallel SVM blasting vibration intelligent prediction model based on the Spark parallel computing framework. the blasting vibration velocity and frequency of blasting construction of a project in southwest are selected and compared with the calculated and measured values of the traditional Sadovski’s formula to verify the intelligent blasting prediction model in the big data environment. the practice shows that blasting vibration intelligent prediction has high efficiency and higher accuracy than traditional models based on parallel SVM used in large data environment. In this paper, the parallel computing and data mining technologies of big data clusters are applied to intelligent prediction of blasting vibrations, changed the traditional random sampling and single mining analysis models, and extracted the useful information for management, decision-making and production from massive data, improved the efficiency and precision of the intelligent blasting prediction models. © 2024 Copyright held by the owner/au

关键词： Vibration analysis

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Domain Decomposition Preconditioners for Unstructured Network Problems in parallel Vector architectures 21

Domain Decomposition Preconditioners for Unstructured Networ...

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50th international conference on parallel processing (ICPP)

作者： Maldonado, Daniel Adrian Schanen, Michel Pacaud, Francois Anitescu, Mihai Argonne Natl Lab Lemont IL 60439 USA

ISBN: (纸本)9781450384414

In this paper we present our experience implementing domain decomposition preconditioners on vector architectures. In particular, we will focus on the solution of unstructured network equations arising from electrical power systems by preconditioning iterative algorithms with the Additive Schwarz Method (ASM). the implementation will be carried out using the Julia programming language, which allows for easy prototyping and interfacing with GPU architectures thanks to its multiple dispatch features. In our experiments, we will show the trade-off between device throughput and convergence of the iterative algorithm as the size of the domain varies, and determine optimal fronts of computational performance.

关键词： Iterative methods

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Re-structuring CNN using quantum layer executed on FPGA hardware for classifying 2-D data

Re-structuring CNN using quantum layer executed on FPGA hard...

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international conference on Integrated Circuits, Design, and Verification (ICDV)

作者： Nhat Hoang Bach Le Ha Vu Dinh Lam Tran thanh Toan Dao thi thu Hong Luu Duy Ninh Nguyen Institute of Electronics Academy of Science and Technology Hanoi Vietnam Electronic department University of Transport and Communications Hanoi Vietnam

ISBN: (数字)9798350371864

ISBN: (纸本)9798350371871

the article proposes a solution to restructure Convolutional Neural Network (CNN) architectures by integrating parameter quantization techniques with traditional CNN models capable of deployment on Field-Programmable Gate Array (FPGA) hardware for evaluating the classification performance of two-dimensional data in real-world scenarios. the solution introduces an additional quantum layer before the final classification layer of the CNN to receive standardized outputs, followed by computations in the Hilbert vector space to generate probability values for assessing classification results. the quantization process helps the model swiftly identify data features while optimizing the parallel computing capability of FPGA hardware. the model is evaluated on the MNIST handwritten digit dataset, revealing two advantages: time-processing on FPGA is four times faster compared to using only the Central processing Unit (CPU) on the PynQ-z2 kit board; classification accuracy is higher when utilizing the quantum layer compared to without it, with the same number of training iterations. these results demonstrate the feasibility of hardware-accelerated AI algorithms combined with quantum algorithms in real applications.

关键词： Quantization (signal) Computational modeling Hardware Data models Vectors Central processing Unit Convolutional neural networks

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A Mini-model can Make Machine Unlearning Better 24th

A Mini-model can Make Machine Unlearning Better

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24th international conference on algorithms and architectures for parallel processing, ICA3PP 2024

作者： Zhao, Mingkang Yu, Weng Zhu, Congcong China University of Geosciences Wuhan China Ministry of Education Key Laboratory of Ethnic Language Intelligent Analysis and Security Governance School of Information Engineering Beijing China Hainan International College of Minzu University of China Li’an International Education Innovation pilot Zone Hainan572499 China City University of Macau 999078 China

ISBN: (纸本)9789819615247

In recent years, with the development of machine learning, plenty of personal data have been utilized in the training process of the models which incurs severe privacy leakage in the field. Current regulations mandate the removal of private user information from both databases and machine learning models upon specific deletion requests. While wiping data records from memory storage is a straightforward task, eliminating the influence of specific data samples from an already-trained model is challenging. Numerous studies in machine unlearning focus on mitigating the impact of target data by adjusting model parameters in deep learning. However, existing methods for data removal in deep learning often fall short of meeting real-world practicality. the intricacies of deep neural networks make unlearning in deep learning a less expedient process than retraining from scratch. For example, some methods require a ton of matrix calculations or even more complicated computations, and some algorithms need a lot of space, which ends up hindering their effectiveness in real-world applications. Accordingly, we’ve come up with a more practical solution. Our method just needs a small part of the validation dataset to pre-train a mini-model to update the parameters of the target model quickly. With this assistant model, we can quickly and accurately unlearn target classes and items. We prove that our proposed method is highly effective in unlearning tasks with not very large amounts of data. © the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Information leakage

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Impact of AVX-512 Instructions on Graph Partitioning Problems 21

Impact of AVX-512 Instructions on Graph Partitioning Problem...

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50th international conference on parallel processing (ICPP)

作者： Hossain, Md Maruf Saule, Erik Univ North Carolina Charlotte Charlotte NC 28223 USA

ISBN: (纸本)9781450384414

Graph analysis now percolates society with applications ranging from advertising and transportation to medical research. the structure of graphs is becoming more complex every day while they are getting larger. the increasing size of graph networks has made many of the classical algorithms reasonably slow. Fortunately, CPU architectures have evolved to adjust to new and more complex problems in terms of core-level parallelism and vector-level parallelism (SIMD-level). In this paper, we are exploring how the modern vector architecture of CPUs can help with community detection, partitioning, and coloring kernels by studying two representatives algorithms. We consider the Intel SkylakeX and Cascade Lake architectures, which support gather and scatter instructions on 512-bit vectors. the existing vectorized graph algorithms of classic graph problems, such as BFS and PageRank, do not apply well to community detection;we show the support of gather and scatter are necessary. In particular for the implementation of the reduce-scatter patterns. We evaluate the performances achieved on the two architectures and conclude that good hardware support for scatter instructions is necessary to fully leverage the vector processing for graph partitioning problems.

关键词： Graph Coloring Community Detection Vector processing AVX-512 Cascade Lake SkylakeX reduce-scatter

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Optimizing Vo-Viso: A Modified Methodology to parallel Computing with Isolating Data in Memristor Arrays 20th

Optimizing Vo-Viso: A Modified Methodology to Parallel Comp...

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20th IFIP WG 10.3 international conference on Network and parallel Computing, NPC 2024

作者： Wang, Wenqing Chen, Yabo Xu, Nuo Hu, Yihong Huang, Chenglong Wei, Shaojun Fang, Liang National University of Defense Technology Changsha410073 China Tsinghua University Beijing100084 China

ISBN: (纸本)9789819628292

the MAGIC NOR gate-based memristor array is a promising processing-in-memory (PIM) approach due to its massive parallelism, flexible logical operation, and non-volatile memory characteristics. the Vo-Viso MAGIC NOR gate operation mode is proposed to achieve high-throughput parallel computing and isolate other data within a memristor array. However, Viso has a cumulative effect on the node voltage of the active row, calling into question the feasibility of Vo-Viso operation mode. In this paper, circuit analysis defines the necessary circuit parameter conditions for enabling parallel computing and isolation units in the MAGIC NOR gate array. By algorithms in Python and CUDA C++ exploration, we determined that achieving the necessary conditions within the array parameters ranges—including the tolerance margin VΔ, array size, Vo, Viso and memristor parameters suitable for real-world circuit requirements—is unfeasible. In response to these challenges, we modified the memristor array architecture. the modified architecture employs transistors to activate compute units while safeguarding the rest selectively. the feasibility of this architecture is validated by SPICE with selected transistors fabricated using a 65 nm process, taking into account transistor resistance and the fluctuations in Vset and Vreset in the 8×8 modified memristor array. To accommodate the design requirement of the state-of-the-art memristor array, the feasibility of 64×64 modified memristor array, taking into account the impact of wire resistance, is further verified. this paper bridges the gap between reliable high-throughput parallel computing operation and MAGIC NOR PIM architecture. © IFIP international Federation for Information processing 2025.

关键词： SPICE

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Advanced HLS for Reconfigurable Image processing in Big Data Systems 12th

Advanced HLS for Reconfigurable Image Processing in Big Da...

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12th international conference on Big Data and Artificial Intelligence, BDA 2024

作者： Bhagirath, K. Pant, Dheeraj Tiwari, Abhishek Khaneja, Vivek Noida201309 India

ISBN: (纸本)9783031818202

this paper introduces novel HLS techniques for reconfigurable and memory-efficient image processing within deep learning frameworks, addressing inherent limitations of current deep learning accelerators (DLAs) due to their dependency on the host processor, leading to pipeline delays and reduced throughput. the proposed approach emphasizes parallelization, on-chip buffering, and scalability, enhancing computational efficiency and throughput for AI applications in big data and edge computing environments. Methodologically, the paper emphasizes mathematical analysis, hardware architecture specification, HLS modeling, Verilog RTL implementation. By addressing these challenges, this work contributes to advancing the performance capabilities of DLAs in deep learning inference tasks. the algorithms integrates seamlessly with DLA IP subsystems, such as AXI interfaces, external (DRAM) and internal (SRAM) memory interfaces, and activation/pooling engines. Key contributions include advanced algorithm design to enhance memory efficiency and reconfigurability, essential for adapting to diverse hardware architectures. Experimental validation demonstrates substantial improvements in computational speed and resource utilization compared to traditional methods, making it suitable for intensive AI tasks in big data analytics. In conclusion, this research presents a framework for integrating HLS techniques into hardware accelerators, facilitating efficient image processing across diverse applications in big data and edge computing. these advancements aim to bolster DLAs’ capabilities in handling complex AI workloads effectively, promising enhanced solutions for AI-driven domains. © the Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Deep learning

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Crop Classification Methods Based on Siamese CBMM-CNN architectures Using Hyperspectral Remote Sensing Data 24th

Crop Classification Methods Based on Siamese CBMM-CNN Archi...

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24th international conference on algorithms and architectures for parallel processing, ICA3PP 2024

作者： Xie, Bin Zhang, Jiahao Li, Yuling Li, Yusong Dong, Xinyu College of Computer and Cyber Security Hebei Normal University Hebei Shijiazhuang China Hebei Provincial Key Laboratory of Network and Information Security Hebei Normal University Hebei Shijiazhuang China Hebei Provincial Engineering Research Center for Supply Chain Big Data Analytics and Data Security Hebei Normal University Hebei Shijiazhuang China

ISBN: (纸本)9789819615278

Amidst global population growth and escalating food demands, real-time agricultural monitoring is crucial for ensuring food security. During the initial stages of crop growth, however, it faces significant challenges in obtaining accurate ground truth data via remote sensing, thereby impeding effective crop classification. Traditional Convolutional Neural Network (CNN) models, although effective in image processing and feature extraction within computer vision, are notably limited in their ability to handle the high dimensionality and complex spectral information inherent in hyperspectral non-image remote sensing data. To address this problem, we designed an enhanced CNN model, CBM-CNN. the CBM-CNN incorporates additional convolutional layers (C), batch normalization (B), and MLP(M) to convert one-dimensional data into two-dimensional data for classification, thus improving the processing efficiency of highly nonlinear data features. Building on CBM-CNN, we add multiple attention mechanisms (CBMM-CNN) to enhance feature extraction capabilities. the Siamese CBMM-CNN (SCBMM-CNN) is employed for in-depth learning of data features, with supervised learning precisely adjusting the model to improve classification performance. Experimental results on hyperspectral remote sensing datasets demonstrate that SCBMM-CNN outperforms traditional machine learning models (PCA-RF, GBDT, GMO-SVM, Random Forest, Decision Tree) and deep learning models (CNN, CNN-LSTM) in terms of accuracy, recall rate, F1 score, and kappa coefficient. these results confirm that SCBMM-CNN significantly improves crop classification accuracy and provides a novel method for early crop growth classification. © the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Convolutional neural networks

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