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检索条件"任意字段=9th International Conference on Algorithms and Architectures for Parallel Processing"

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A Distributed and parallel Tensor Hierarchical Tucker Decomposition on Clouds 9

A Distributed and Parallel Tensor Hierarchical Tucker Decomp...

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9th international conference on Advanced Cloud and Big Data, CBD 2021

作者： Ning, Weikai Wu, Zebin Sun, Jin Yang, Jiandong Zhang, Yi Zhu, Yaoqin Wei, Zhihui Xia, Lei Nanjing University of Science and Technology School of Computer Science and Engineering Nanjing China China Satellite Maritime Tracking and Control Department Jiangyin China China Railway Shanghai Group Co. Ltd Shanghai China

ISBN: (纸本)9781665407458

Hierarchical Tucker decomposition is widely used in image processing, data mining and many other fields. With the increase of data volumes, the hierarchical Tucker decomposition requires much more amounts of memories and computing capacities, beyond the computing resources of a single computer. Accordingly, we propose a distributed and parallel tensor hierarchical Tucker decomposition on a cloud computing platform. Both coarse-grained parallelism and fine-grained parallelism are exploited in the hierarchical Tucker decomposition by splitting the computation tasks on the dimension tree nodes. Each individual node in the dimension tree is independent on the tree topology and can thus be executed in parallel. Experimental results indicate that the proposed method is effective in processing high-dimensional tensor data with significant speedups and high robustness. © 2022 IEEE.

关键词： Tensors

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An overview of parallel processing of rectangular determinant calculation

An overview of parallel processing of rectangular determinan...

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Mediterranean conference on Embedded Computing (MECO)

作者： Besnik Duriqi Halil Snopçe Armend Salihu Artan Luma Faculty of Computer Science South East European University - SEEU Republic of North Macedonia Faculty of Computer Science Republic of North Macedonia Department of Computer Science UNI Universum International College Prishtina Republic of Kosovo

ISBN: (数字)9798350387568

ISBN: (纸本)9798350387575

this paper focuses on developing algorithms for parallel determinant processing, a crucial task in linear algebra and computational mathematics. the aim is to improve efficiency in high-performance computing environments by designing and analyzing algorithms that use parallel processing to expedite determinant computation for various matrices range. the research explores methods like Laplace expansion, LU decomposition, eigenvalue decomposition, Gaussian elimination, and cofactor expansion, assessing their efficiency, scalability, and applicability in different computational environments. the study employs advanced parallel programming techniques and architectures, utilizing multi-core processors with the focus aim into utilization of Chio’s method of rectangular determinants processing in parallel etc. the research also investigates the mathematical underpinnings of parallel determinant algorithms, addressing challenges like load balancing, data distribution, and synchronization. the results show significant improvements in determinant calculations efficiency, reducing computation times for large matrices.

关键词： Multicore processing parallel programming Scalability Signal processing algorithms Computer architecture Linear algebra parallel processing

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Efficient, Out-of-Memory Sparse MTTKRP on Massively parallel architectures 22

Efficient, Out-of-Memory Sparse MTTKRP on Massively Parallel...

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36th ACM international conference on Supercomputing (ICS)

作者： Nguyen, Andy Helal, Ahmed E. Checconi, Fabio Laukemann, Jan Tithi, Jesmin Jahan Soh, Yongseok Ranadive, Teresa Petrini, Fabrizio Choi, Jee W. Univ Oregon Eugene OR 97403 USA Intel Labs Hillsboro OR USA Univ Erlangen Nurnberg Erlangen Germany Lab Phys Sci College Pk MD USA

ISBN: (纸本)9781450392815

Tensor decomposition (TD) is an important method for extracting latent information from high-dimensional (multi-modal) sparse data. this study presents a novel framework for accelerating fundamental TD operations on massively parallel GPU architectures. In contrast to prior work, the proposed Blocked Linearized CoOrdinate (BLCO) format enables efficient out-of-memory computation of tensor algorithms using a unified implementation that works on a single tensor copy. Our adaptive blocking and linearization strategies not only meet the resource constraints of GPU devices, but also accelerate data indexing, eliminate control-flow and memory-access irregularities, and reduce kernel launching overhead. To address the substantial synchronization cost on GPUs, we introduce an opportunistic conflict resolution algorithm, in which threads collaborate instead of contending on memory access to discover and resolve their conflicting updates on-the-fly, without keeping any auxiliary information or storing non-zero elements in specific mode orientations. As a result, our framework delivers superior in-memory performance compared to prior state-of-the-art, and is the only framework capable of processing out-of-memory tensors. On the latest Intel and NVIDIA GPUs, BLCO achieves 2.12 - 2.6x geometric-mean speedup (with up to 33.35x speedup) over the state-of-the-art mixed-mode compressed sparse fiber (MM-CSF) on a range of real-world sparse tensors.

关键词： Tensor decomposition MTTKRP sparse tensors sparse formats parallel performance GPU

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Efficiently Computing Maximum Clique of Sparse Graphs with Many-Core Graphical processing Units

Efficiently Computing Maximum Clique of Sparse Graphs with M...

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19th international conference on Software Technologies, ICSOFT 2024

作者： Cardone, Lorenzo Di Martino, Salvatore Quer, Stefano Politecnico di Torino Turin Italy

ISBN: (纸本)9789897587061

the Maximum Clique is a fundamental problem in graph theory and has numerous applications in various domains. the problem is known to be NP-hard, and even the most efficient algorithm requires significant computational resources when applied to medium or large graphs. To obtain substantial acceleration and improve scalability, we enable highly parallel computations by proposing a many-core graphical processing unit implementation targeting large and sparse real-world graphs. We developed our algorithm from CPUbased solvers, redesigned the graph preprocessing step, introduced an alternative parallelization scheme, and implemented block-level and warp-level parallelism. We show that the latter performs better when the amount of threads included in a block cannot be fully exploited. We analyze the advantages and disadvantages of the proposed strategy and its behavior on different graph topologies. Our approach, applied to sparse real-world graph instances, shows a geomean speed-up of 9x, an average speed-up of over 19x, and a peak speed-up of over 70x, compared to a parallel implementation of the BBMCSP algorithm. It also obtains a geometric mean speed-up of 1.21x and an average speed-up of over 2.0x on the same graph instances compared to the parallel implementation of the LMC algorithm. © 2024 by SCITEPRESS – Science and Technology Publications, Lda.

关键词： Graph algorithms

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Embedding (K9-C9)n into Certain Necklace Graphs 7th

Embedding (K9-C9)n into Certain Necklace Graphs

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7th international conference on Big Data and Cloud Computing Challenges, ICBCC 2022

作者： Afiya, Syeda Rajesh, M. School of Advanced Sciences Vellore Institute of Technology Tamilnadu Chennai India School of Computer Science and Engineering Vellore Institute of Technology Tamilnadu Chennai India

ISBN: (纸本)9789819910502

In parallel and distributed computing, there are practically two networks: linear networks (also called paths) and rings (also called loops). Many efficient algorithms, such as signal and image processing, were first discovered by solving algebraic problems, graphical problems and parallel implementations involving linear networks and rings. As a result, a network having both good path and cycle embedding is crucial. In this paper, using embedding method, we simulate the cartesian product of (K9-C9)n graph into certain necklace graphs. © 2023, the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Linear networks

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Hardware-Efficient Ultrasonic Entrance Counting: Comparing Different Machine Learning Approaches 26

Hardware-Efficient Ultrasonic Entrance Counting: Comparing D...

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26th international conference on Pattern Recognition / 8th international Workshop on Image Mining - theory and Applications (IMTA)

作者： Langer, Tim Waschneck, Bernd Partzsch, Johannes Kelber, Florian Mayr, Christian Infineon Technol Dresden GmbH Co KG Dresden Germany Fraunhofer Inst Integrated Circuits Div Engn Adapt Syst Dresden Dresden Germany Tech Univ Dresden Chair Highly Parallel VLSI Syst & Neuro Microelec Dresden Germany

ISBN: (数字)9781665490627

ISBN: (纸本)9781665490627

In this work, the classification of walking direction based on ultrasonic signals has been examined for entrance counting. Feed-forward and recurrent neural network architectures as well as simpler machine learning techniques have been investigated and compared with classical signal processing techniques. Using only a single ultrasonic receiver, the focus was set on the development of a hardware-efficient system concept. Different ultrasonic measurement methods in time and frequency domain have been compared with the perspective of a holistic energy optimization. the analysis of the system's hardware efficiency was completed by an estimation of algorithmic latency, energy and storage consumption based on the arithmetic of the classification algorithms. All algorithms showed an estimated energy consumption of less than 10 mu J for a single inference on a state-of-the-art implementation of an ARM (R) Cortex (R) M4F micro-controller, which was found to be negligible compared to the energy of the measurement principle. Compared to other sensor types and multi-sensor systems, a state-of-the-art test accuracy of 99.72% could be achieved for differentiating between the two entrance directions of a present person and the absence of a person.

关键词： Entrance Counting Ultrasound Machine Learning Edge Computing Low Power TinyML Smart Buildings

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Towards Optimized Hydrological Forecast Prediction of WRF-Hydro on GPU 25

Towards Optimized Hydrological Forecast Prediction of WRF-Hy...

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25th IEEE international conferences on High Performance Computing and Communications, 9th international conference on Data Science and Systems, 21st IEEE international conference on Smart City and 9th IEEE international conference on Dependability in Sensor, Cloud and Big Data Systems and Applications, HPCC/DSS/SmartCity/DependSys 2023

作者： Liu, Hongrui Lei, Kelun Yang, Hailong Luan, Zhongzhi Qian, Depei School of Computer Science and Engineering Beihang University Beijing China

ISBN: (纸本)9798350330014

Hydrological models are designed to simulate and predict the dynamic cycling of surface and groundwater. these models represent simplifications of complex hydrological pro-cesses and play an integral role in hydrological research and real-world applications. the WRF Hydro model is widely used due to its multi-scale capabilities for land-atmosphere modeling. Recent studies have focused on enhancing the performance of different modules in WRF through GPU parallel optimization techniques. However, WRF - Hydro has not been able to utilize the GPU for computations which leads to lower computational efficiency when simulating hydrological calculations over large regions for extended periods. In this paper, we first analyze the computational and communication bottlenecks in WRF Hydro. We then propose several methods for performance optimization accordingly. To address the computational bottleneck, we develop efficient GPU-based overland routing and channel routing, eliminating redundant calculations. Additionally, we adopt an improved block partitioning strategy to enhance memory access efficiency on the GPU. To tackle the communicational bottleneck, we adopt a packetized communication strategy to reduce the number of communication operation calls in channel routing and simplify the preprocessing operations for communication. Meanwhile, for overland routing, we employ multi-stream to minimize redundant synchronization operations and overlap communication with computation to reduce communication overhead. the evaluation results demonstrate that WRF -Hydro can achieve significant speedups in several simulation cases after applying our proposed optimizations, resulting in a maximum speedup of 6.67 ×. © 2023 IEEE.

关键词： Graphics processing unit

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Efficient Computing for Reduced Density Matrix on GPUs 25

Efficient Computing for Reduced Density Matrix on GPUs

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作者： Liang, Wenhao Jin, Runfeng Tian, Yingqi Ma, Yingjin Jin, Zhong Computer Network Information Center Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China School of Chemistry and Chemical Engineering Nanjing University Nanjing China

ISBN: (纸本)9798350330014

the reduced density matrix (RDM) plays an important role in quantum physics. With the RDM, we can accurately describe the energy of the quantum system. However, solving the RDM is a computationally intensive task where matrix multiplication accounts for more than 95% of the computation time, and exponential complexity, large memory consumption, and tensor sparsity make it challenging to achieve efficient computation. this paper proposes an efficient, scalable and multi-GPU solver for computing the RDM. the complexity of computing RDM is reduced to polynomial by using a tensor network approach in the form of matrix product state (MPS). the sparsity blocks are composed of contiguous memory locations using the list algorithm. the precomputation approach uses a small memory overhead to replace some redundant computations. Furthermore, the sparsity blocks are computed on the GPU using variable-size batch general matrix multiplication (GEMM). We benchmark the performance using a water molecule, and our results show that we achieve a 22.4 × speedup when using four MI50 GPUs compared to a 32-core CPU. Additionally, we demonstrate excellent strong scaling, achieving over 92% parallel efficiency when comparing the performance on 256 nodes versus 16 nodes. © 2023 IEEE.

关键词： Graphics processing unit

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A Bandwidth-Adaptive On-Chip Storage Network Architecture

A Bandwidth-Adaptive On-Chip Storage Network Architecture

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international conference on Integrated Circuits and Microsystems (ICICM)

作者： Kou Wang Ningmei Yu Dian Tian Liang Yang Peng Wang Minghui Xie School of Automation and Information Engineering Xi'an University of Technology Xi'an China Electronics Department University of Alcalá Alcalá de Henares Madrid Spain

ISBN: (数字)9798331509453

ISBN: (纸本)9798331520243

A scalable bandwidth-adaptive on-chip storage network architecture is proposed to address the severe data conflict and low bus parallelism in existing multi-level storage, Crossbar, and NoC architectures in edge accelerated computing. this architecture combines the advantages of centralized and distributed memory, allowing the memory hierarchy to be flexibly adapted based on current computational needs and memory access patterns to better accommodate multi-core processors and parallel computing requirements. this paper designs the result visualization method to visualize the stress of storing each node and bus. Furthermore, the full path test incentive is intended for the secondary sharing policy and router. the feasibility of this paper's architecture is verified through VCS simulation and visualization analysis.

关键词： Structural rings Multicore processing Memory management Bandwidth Network architecture parallel processing System-on-chip Stress Testing Periodic structures

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PimCity: A Compute in Memory Substrate featuring both Row and Column parallel Computing 8

PimCity: A Compute in Memory Substrate featuring both Row an...

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8th IEEE international conference on Rebooting Computing, ICRC 2023

作者： Resch, Salonik Cilasun, Husrev Zabihi, Masoud Chowdhury, Zamshed Zhao, Zhengyang Wang, Jian-Ping Sapatnekar, Sachin S. Karpuzcu, Ulya University of Minnesota Twin Cities United States

ISBN: (纸本)9798350382044

processing-in-memory (PIM) substrates can perform parallel computation directly within the memory array. As a result, throughput performance and energy efficiency can reach unprecedented levels, however, there are limitations. Typical PIM architectures only support parallel computing in one dimension of the memory array: Computation is performed along either multiple rows or multiple columns (but not both). this restricts data layout and makes intra-array intermediate data transfers during computation inevitable - which require reads and writes, even for short-distance data movement. Inter-array data transfers, on the other hand, become a problem for larger scale algorithms which use more than one PIM array. Such data transfers incur large communication overheads and increase the complexity of the peripheral circuitry and interconnection network between arrays. Intermediate data transfers of any form limit scalability and efficiency. To overcome this limitation, we introduce PimCity, a new PIM substrate which can compute in both the rows and the columns of the memory array. PimCity replaces intraarray data transfer (memory) operations with lower overhead logic operations inside the memory array. Further, PimCity can perform logic operations directly across neighboring memory arrays, which in turn enables low-cost inter-array data transfers. PimCity hence represents a scalable PIM architecture suitable for both HPC and embedded IoT style applications. © 2023 IEEE.

关键词： Data transfer

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