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检索条件"任意字段=9th International Conference on Algorithms and Architectures for Parallel Processing"

共 2826 条记录，以下是151-160 订阅

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parallel Vectorized Implementations of Compensated Summation algorithms 1

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14th international conference on parallel processing and Applied Mathematics, PPAM 2022

作者： Dmitruk, Beata Stpiczyński, Przemyslaw Maria Curie-Sklodowska University Institute of Computer Science ul. Akademicka 9 Lublin20-031 Poland

ISBN: (数字)9783031304453

ISBN: (纸本)9783031304446

the aim of this paper is to show that Kahan’s and Gill-Møller compensated summation algorithms that allow to achieve high accuracy of summing long sequences of floating-point numbers can be efficiently vectorized and parallelized. the new implementation uses Intel AVX-512 intrinsics together with OpenMP constructs in order to utilize SIMD extension of modern multicore processors. We describe in detail the vectorization technique and show how to define custom reduction operators in OpenMP. Numerical experiments performed on a server with Intel Xeon Gold 6342 processors show that the new implementations of the compensated summation algorithms achieve much better accuracy than ordinary summation and their performance is comparable with the performance of the ordinary summation algorithm optimized automatically. Moreover, the experiments show that the vectorized implementation of the Gill-Møller algorithm is faster than the vectorized implementation of Kahan’s algorithm. © 2023, the Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Digital arithmetic

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LSSM-SpMM: A Long-Row Splitting and Short-Row Merging Approach for parallel SpMM on PEZY-SC3s 24th

LSSM-SpMM: A Long-Row Splitting and Short-Row Merging Appro...

引用

24th international conference on algorithms and architectures for parallel processing, ICA3PP 2024

作者： Cao, Ligang Wang, Qinglin Yang, Shun Xia, Rui Guo, Weihao Liu, Jie Laboratory of Digitizing Software for Frontier Equipment National University of Defense Technology Changsha410073 China National Key Laboratory of Parallel and Distributed Computing National University of Defense Technology Changsha410073 China

ISBN: (纸本)9789819615506

Sparse Matrix-Dense Matrix Multiplication (SpMM) is a crucial kernel used in a wide range of fields including machine learning and linear algebra solvers. thus, enhancing the performance of SpMM is essential. the uneven distribution of non-zeros in sparse matrices and the tight data dependency between sparse and dense matrices make efficiently running SpMM on various hardware platforms challenging. To address these issues, optimisations are tailored according to the characteristics of the different hardware platforms. In this study, we propose a Long Row Split and Short Row Merge (LSSM) approach on the new MIMD computing platform PEZY-SC3s, utilising the standard Compressed Sparse Row (CSR) format to optimise SpMM. Specifically, LSSM divides the rows of the sparse matrix into short rows (rows with a number of non-zeros less than blockSize) and long rows (rows with a number of non-zeros greater than blockSize), applying splitting to the long rows and merging to the short rows to optimize their computations separately. Additionally, based on the hardware features of PEZY-SC3s, we employed the atomic cache for workload scheduling, SIMD instructions to accelerate computation, and Local Memory to reduce data read-write operations, addressing issues of poor data locality, workload imbalance, and vectorisation during SpMM execution. As the first study of SpMM on PEZY-SC3s, compared with BS-SpMM and RoDe-SpMM implemented on PEZY-SC3s, LSSM-SpMM offers up to 26.17× and 13.59× acceleration on the SuiteSparse and deep learning datasets, respectively, with geometric mean speedups of 1.56× and 1.71×. © the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Deep learning

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Language-Based Colorization with Sparse Attention and Multi-scale Cross-Modal Semantic Alignment 24th

Language-Based Colorization with Sparse Attention and Mult...

引用

24th international conference on algorithms and architectures for parallel processing, ICA3PP 2024

作者： Zhang, Ying Gao, Yutong Liu, Xuan Zhang, Lefeng Liu, Xianggan Jiang, Shan Ethnic Language Intelligent Analysis and Security Governance Minzu University of China Beijing China Faculty of Data Science City university of Macau China Natural Language Processing and Knowledge Graph Lab Huazhong University of Science and Technology Wuhan China

ISBN: (纸本)9789819615476

Language-based colorization generates realistic and aesthetically appealing colors by leveraging the guidance of intuitive and user-friendly natural language descriptions. Previous methods in language-based image colorization face several significant challenges, including limited color richness, color bleeding, color distortions, and inconsistent color styles. these issues often arise due to the reliance on dense attention mechanisms, which can lead to an overemphasis on global features at the expense of local details. Furthermore, many feature fusion modules for text and grayscale images are not designed to achieve adequate alignment of the diverse feature representations, resulting in suboptimal colorization outcomes. In this paper, we explore a novel module that employs sparse attention to mitigate the issue of color bleeding and limited colorfulness in image colorization tasks. By introducing a sparse attention mechanism, our method enables more flexible allocation of computational resources with a focus on color awareness. Additionally, we propose a module that effectively aligns grayscale images with color descriptions, thereby improving the consistency and quality of the colorization results. this module leverages the synergy between image features and language descriptions to solve long-standing issues like color bleeding. Empirical evaluations demonstrate that our approach surpasses recent state-of-the-art techniques in both automatic and language-based colorization tasks, validating the effectiveness and robustness of our proposed method in generating high-quality, visually appealing colorized images. © the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Semantics

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An Improved Ant Colony Algorithm Accelerated by GPU in Track Correlation

An Improved Ant Colony Algorithm Accelerated by GPU in Track...

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6th international conference on Intelligent Computing and Signal processing (ICSP)

作者： Xu Chen Xianzhao Shen Qingchen Zhou Mingming Xu East China Research Institute of Electronic Engineering Hefei City Anhui China

In the distributed information fusion system, the problem of track correlation can be transformed into the problem of multi-dimension assignment. However, it9;s a NP-Hard problem. In view of the low convergence-rat... 详细信息

ISBN: (数字)9798350376548

ISBN: (纸本)9798350376555

In the distributed information fusion system, the problem of track correlation can be transformed into the problem of multi-dimension assignment. However, it's a NP-Hard problem. In view of the low convergence-rate and the more iterations for the existing methods, a kind of improved ant colony parallel solution algorithm with the advantages of small-scale searches, fast convergence speed, less iteration has been put forward. Firstly, the multi-dimension assignment model of track correlation should be established based on grey theory. Secondly, the search area is narrowed down to get higher searching efficiency through updating the search listings based on the neighbourhood of the maximum grey relational coefficient, and the pheromones are updated using the wolves assignment principle for reference in order to avoid trapping in local optimum. At last, use the parallel strategy of GPU acceleration to realize the improved algorithm. the simulation results show that the improved algorithm can obtain the correct association rate of more than 90% by ten iterations or less in one association period; In addition, the parallel solving strategy based on GPU acceleration can improve the solving efficiency, and the acceleration result is more obvious with the number of targets increasing.

关键词： Correlation coefficient Correlation Target tracking NP-hard problem Simulation Signal processing algorithms Graphics processing units Signal processing Search problems Convergence

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Temporal Transformation Network Based On Scale Sequences for Cloth-Changing Person Re-Identification in Video Datasets 9

Temporal Transformation Network Based On Scale Sequences for...

引用

9th international conference on Computer and Communications, ICCC 2023

作者： Zhu, Xiaoke Zhao, Bo Dong, Zhiwei Dong, Lingyun Li, Danyang School of Computer and Information Engineering Henan University Kaifeng China Henan University Henan Engineering Research Center of Intelligent Technology and Application China Henan Key Laboratory of Big Data Analysis and Processing Henan University Kaifeng China

ISBN: (纸本)9798350317251

this paper introduces the Temporal Transform Network based on Scale Sequences (TTS) for cloth-changing person re-identification in video datasets. the TTS network is designed to capture multi-scale temporal cues within video sequences. It accomplishes this by initially modeling short-term temporal cues between adjacent frames, followed by capturing long-term relationships between non-consecutive frames. In more detail, short-term temporal cues are modeled through parallel inflated convolutions with different time dilation rates, enabling the representation of pedestrian movement and appearance dynamics. Long-term relationships are effectively captured using a temporal self-attention model, mitigating challenges such as occlusion and noise within the video sequence. the TTS network outperforms existing methods across cloth-changing video ReID datasets such as CCVID. For instance, under general settings, our approach exhibits a 1.1% improvement in top-1 accuracy and a corresponding 1.1% increase in mAP compared to the baseline. In cloth-changing settings, we observe a 0.2% enhancement in top-1 accuracy and a notable 1.3% increase in mAP relative to the baseline. © 2023 IEEE.

关键词： Video recording

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Comparative Analysis of Various CNN architectures in Recognizing Objects in a Classification System

Comparative Analysis of Various CNN Architectures in Recogni...

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international conference for Convergence of Technology (I2CT)

作者： Yash Surve Kshitija Pudari Sonali Bedade Balaji Durai Masanam Kinnari Bhalerao Pratik Mhatre Department of Electronics and Telecommunication Engineering Vidyalankar Institute of Technology Mumbai India

ISBN: (数字)9798350394474

ISBN: (纸本)9798350394481

Object recognition, an essential technique in computer vision, enables machines to identify and understand real-time objects and environments based on input images. the main aim of this technology is to accurately recognize image features to enable accurate object recognition. With the rapid evolution of various machine learning (ML) and deep learning (DL) algorithms, the world of image processing and computer vision has witnessed significant growth. Deep learning algorithms offer high accuracy by processing vast amounts of data, while machine learning algorithms provide flexibility in selecting the best combinations of features and classifiers for learning purposes. Convolutional Neural Network (CNN) is a widely used deep-learning model that is highly effective in classifying images. AlexNet, VGG16, ResNet and GoogleNet are some of the well-known CNN architectures used for object recognition. the paper proposes a comparative analysis of prediction accuracy between these pre-trained CNN models using transfer learning. the transfer learning approach, on the other hand, involves the fine-tuning of pre-trained models to enhance prediction accuracy in various image classification scenarios. In this paper, the CNN models are trained and tested on a dataset containing images of apples, oranges and bananas. Experimental results with a real dataset show that MobileNet V2 has the highest accuracy of 92.80%.

关键词： Training Analytical models Machine learning algorithms Transfer learning Predictive models Data models Convolutional neural networks

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Halide Code Generation Framework in Phylanx 28th

Halide Code Generation Framework in Phylanx

引用

28th international European conference on parallel and Distributed Computing , Euro-Par 2022

作者： Tohid, R. Shirzad, Shahrzad Taylor, Christopher Sakin, Sayef Azad Isaacs, Katherine E. Kaiser, Hartmut Center for Computation and Technology Louisiana State University Baton Rouge United States Tactical Computing Labs Muenster United States SCI Institute University of Utah Salt Lake City United States

ISBN: (纸本)9783031312083

Separating algorithms from their computation schedule has become a de facto solution to tackle the challenges of developing high performance code on modern heterogeneous architectures. Common approaches include Domain-specific languages (DSLs) which provide familiar APIs to domain experts, code generation frameworks that automate the generation of fast and portable code, and runtime systems that manage threads for concurrency and parallelism. In this paper, we present the Halide code generation framework for Phylanx distributed array processing platform. this extension enables compile-time optimization of Phylanx primitives for target architectures. To accomplish this, (1) we implemented new Phylanx primitives using Halide, and (2) partially exported Halide’s thread pool API to carry out parallelism on HPX (Phylanx’s runtime) threads. (3) showcased HPX performance analysis tools made available to Halide applications. the evaluation of the work has been done in two steps. First, we compare the performance of Halide applications running on its native runtime with that of the new HPX backend to verify there is no cost associated with using HPX threads. Next, we compare performances of a number of original implementations of Phylanx primitives against the new ones in Halide to verify performance and portability benefits of Halide in the context of Phylanx. © 2023, the Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Array processing

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Exploit Innovative Computer architectures with Molecular Dynamics 4th

Exploit Innovative Computer Architectures with Molecular Dyn...

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4th international conference on Numerical Computations: theory and algorithms, NUMTA 2023

作者： Marchetti, Filippo Gregori, Daniele E4 Computer Engineering via Martiri della Libertà 66 Scandiano Italy INSTM Via G. Giusti 9 Firenze Italy

ISBN: (纸本)9783031812460

Atomistic simulations are a powerful tool to analyse the structure and the behavior of various biological molecules and are widely used in biochemistry studies. Currently, there are several software packages available which provide the algorithms for the numerical resolution of the physical equation necessary for the simulations. those softwares are demanding and need to handle a large amounts of resources, therefore the hardware in use has to be efficient in terms of performance and costs. Here we tested the Molecular Dynamics toolkit Gromacs on different platforms: Intel, AMD and ARM clusters are considered, also with the support of NVIDIA GPUs. During the tests energy consumption is measured in both idle and working case obtaining the energy to solution for every machine. While the highest performances are obtained with Intel we found that AMD and ARM servers are valid option if energy savings is considered alongside performance, the use of GPU gives a remarkable contribution to reduce consumption. © the Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Graphics processing unit

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FPGA Implementation of QC-LDPC Decoder with Rapid Cyclic Shifter for CV-QKD Systems

FPGA Implementation of QC-LDPC Decoder with Rapid Cyclic Shi...

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Communication, Image and Signal processing (CCISP), international conference on

作者： Zeyuan Jin Yinghua Xie Xue-Qin Jiang Genlong Chen School of Information Science and Technology Donghua University Shanghai China

ISBN: (数字)9798350356656

ISBN: (纸本)9798350356663

In continuous variable quantum key distribution (CV-QKD) systems, low-density parity check (LDPC) decoders have gained widespread adoption due to their robust error correction capabilities and good adaptability to parallel processing hardware designs. We introduce a syndrome-based normalized min-sum algorithm (S-NMSA) and implement the decoder on FPGAs for high throughput and minimal resource consumption. the decoder utilizes a semi-parallel architecture. the proposed rapid cyclic shifter (RCS) can complete the shift of any dimension matrix in one clock cycle and realizes a significant reduction in hardware resource consumption. the semi-parallel decoding structure attains a 68.5 Mbps processing throughput on the condition that the system clock of the quasi-cyclic (QC) LDPC decoder is 250 Mhz.

关键词： Phase change materials Signal processing algorithms throughput Parity check codes Hardware Decoding Quantum key distribution Resource management Field programmable gate arrays Clocks

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Implementation of Successive Cancellation Polar Decoder Architecture 20

Implementation of Successive Cancellation Polar Decoder Arch...

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20th IEEE India Council international conference, INDICON 2023

作者： Swaroop, B Sai Arun Kumar, K.D.V.N.B. Teja, Srirangam Sai Vinay Kumar, Sunkavalli Suresh Babu, Manam Ponnu Yamuna, B. Balasubramanian, Karthi Amrita Vishwa Vidyapeetham Amrita School of Engineering Department of Electronics and Communication Engineering Coimbatore India

ISBN: (纸本)9798350305593

Polar codes have been adopted as error correction codes for control channels in 5G New Radio through the 3rd Generation Partnership Project (3GPP) standardization. the main requirement for 5G technology is to support maximum bandwidth and throughput along with low-complex error correction codes of larger block sizes. Polar codes achieve channel capacity closer to the Shannon limit. the challenges involved in the hardware implementation of the polar decoder have made it a widely researched topic in recent times. Different hardware architectures have been proposed for successive cancellation and successive cancellation list decoding algorithms. In this work using the semi-parallel successive cancellation decoding architecture, a polar decoder has been designed. In order to realize a system-level design, the decoder has been packaged as an AXI4-Lite IP and integrated into a Zynq-based block design using Rapid Prototyping of Hardware Accelerators on Xilinx FPGAs (RPHAX) framework. the resulting design has been deployed on a PYNQ FPGA. On the software side, the PYNQ framework has been utilized to write inputs to the slave registers and report the corresponding output. the implementation of this design as a soft logic on FPGA enables it to be leveraged by any application running on the processing system. A modification in the decoder architecture has also been attempted that shows a significant reduction in power and number of clock cycles by 50% and 33.64% respectively with an increase in the throughput by 58.3%. © 2023 IEEE.

关键词： FPGA Hardware Implementation Polar Codes Semi-parallel Architecture Successive Cancellation

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