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检索条件"任意字段=9th International Conference on Algorithms and Architectures for Parallel Processing"

共 2830 条记录，以下是161-170 订阅

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An Experimental Analysis of RL based Compiler Optimization Techniques using Compiler GYM

An Experimental Analysis of RL based Compiler Optimization T...

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international conference for Convergence of Technology (I2CT)

作者： Boda Venkata Nikith Shaik Reeha G Mani Prakash Reddy Meena Belwal Dept. of Computer Science & Engineering Amrita School of Computing Amrita Vishwa Vidyapeetham Bengaluru India

ISBN: (数字)9798350394474

ISBN: (纸本)9798350394481

Compiler optimization significantly impacts algorithm performance, whether it may be graph-based, parallel computing workloads and more. Understanding how these algorithms' performance varies under different optimization scenarios is crucial. this study explores diverse Reinforcement Learning (RL) algorithms for code optimization in Compiler Gym, including Actor-Critic, Random Walk, Tabular Q, and a Brute Force approach. three benchmark datasets, Dijkstra, CRC32, and npbv0 from Compiler Gym libraries, and are evaluated using execution time and maximum reward metrics. this study reveals that the npbv0 dataset consistently outperforms others across all RL algorithms, demonstrating its compatibility with RL-based compiler optimization. this research highlights the role of compiler optimization in algorithm performance, emphasizing the potential of RL techniques in diverse workloads, with npbv0 excelling as a benchmark dataset.

关键词： Measurement Codes Force Reinforcement learning Benchmark testing parallel processing Libraries

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9th international conference on Future Data and Security Engineering, FDSE 2022

9th International Conference on Future Data and Security Eng...

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9th international conference on Future Data and Security Engineering, FDSE 2022

ISBN: (纸本)9789811980688

the proceedings contain 57 papers. the special focus in this conference is on Future Data and Security Engineering. the topics include: Preface;towards a Foundation of Web3;covid-19 Detection Based on Lung Lesion Signs in Big Data processing Environment;predicting Loan Repayment Using a Hybrid of Genetic algorithms, Logistic Regression, and Artificial Neural Networks;performance Evaluation of Regular Decomposition and Benchmark Clustering Methods;authentication of Luxury Products – Identifying Key Requirements from a Seller and Consumer Perspective;Analysis of a New Practical SPN-Based Scheme in the Luby-Rackoff Model;authorization and Access Control for Different Database Models: Requirements and Current State of the Art;a Hierarchical Deterministic Wallet Using Ed25519 Digital Signature Scheme;a Secure Framework for Internet of Medical things Security Based System Using Lightweight Cryptography Enabled Blockchain;signature algorithms on Non-commutative Algebras Over Finite Fields of Characteristic Two;design a Smart Lock System Using Fingerprint and Password for Enhancing Security;in-Memory Computing architectures for Big Data and Machine Learning Applications;towards an Attention-Based threat Detection System for IoT Networks;security and Privacy Issues and Solutions in Federated Learning for Digital Healthcare;pPATE: A Pragmatic Private Aggregation of Teacher Ensembles Framework by Sparse Vector Technique Based Differential Privacy, Paillier Cryptosystem and Human-in-the-loop;vietnamese Text’s Writing Styles Based Authorship Identification Model;application of Machine Learning in Malware Detection;text Classification Models and Topic Models: An Overall Picture and a Case Study in Vietnamese;deep Hybrid Models for Forecasting Stock Midprices from the High-Frequency Limit Order Book;an Image Denoising Model Based on Nonlinear Partial Diferential Equation Using Deep Learning;recommendations in E-Commerce Systems Based on Deep Matrix Factorization;AttendanceKit: A s

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AutoFlow: Hotspot-Aware, Dynamic Load Balancing for Distributed Stream processing 21st

AutoFlow: Hotspot-Aware, Dynamic Load Balancing for Distribu...

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21st international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Lu, Pengqi Yue, Yue Yuan, Liang Zhang, Yunquan Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China

ISBN: (纸本)9783030953911;9783030953904

Stream applications are widely deployed on the cloud. While modern distributed streaming systems like Flink and Spark Streaming can schedule and execute them efficiently, streaming dataflows are often dynamically changing, which may cause computation imbalance and back-pressure. We introduce AutoFlow, an automatic, hotspot-aware dynamic load balance system for streaming dataflows. It incorporates a centralized scheduler that monitors the load balance in the entire dataflow dynamically and implements state migrations correspondingly. the scheduler achieves these two tasks using a simple asynchronous distributed control message mechanism and a hotspot-diminishing algorithm. the timing mechanism supports implicit barriers and a highly efficient state-migration without global barriers or pauses to operators. It also supports a time-window based load-balance measurement and feeds them to the hotspot-diminishing algorithm without user interference. We implemented AutoFlow on top of Ray, an actor-based distributed execution framework. Our evaluation based on various streaming benchmark datasets shows that AutoFlow achieves good load-balance and incurs a low latency overhead in a highly data-skew workload.

关键词： Stream processing Big data Data skewness Control message Load balance

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Enhancing Delay-Sensitive Task Offloading: A Multi-agent Deep Reinforcement Learning Algorithm for MEC-Based AIoT Systems 24th

Enhancing Delay-Sensitive Task Offloading: A Multi-agent Dee...

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24th international conference on algorithms and architectures for parallel processing, ICA3PP 2024

作者： Tang, Fengjie Xu, Jia Liu, Xiao Yao, Aiting Fang, Mingyan Li, Xuejun Anhui Provincial International Joint Research Center for Advanced Technology in Medical Imaging School of Computer Science and Technology Anhui University Hefei China School of Information Technology Deakin University Geelong Australia

ISBN: (纸本)9789819615414

Artificial Intelligence of things (AIoT) systems are widely utilized in various domains such as smart logistics and smart health. In AIoT systems, computational tasks earmarked for offloading by IoT devices often have different task priorities and heterogeneous resource requirements. However, these factors will affect the QoS of the solution and the task response time. therefore, motivated by a typical smart warehouse system, a Multi-access Edge Computing (MEC) based distributed task offloading framework is proposed. Afterward, a delay-sensitive mixed-integer programming model is defined to address the imbalanced utilization of computing resources between edge and cloud servers during the offloading process. Finally, based on the attention mechanism, a Priority-Driven Multi-Agent Deep Reinforcement Learning algorithm (PDMA-DRL) is proposed to fulfill real-time resource requirements while reducing the task response time. the PDMA-DRL algorithm consists of two agents, and each agent corresponds to a sub-problem. Comprehensive experimental results demonstrate that our proposed PDMA-DRL algorithm can outperform representative existing methods in generating delay-sensitive task offloading plans and effectively reducing the task response time. © the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Deep reinforcement learning

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Satellite Remote Sensing Application Model parallel Training Technology Research

Satellite Remote Sensing Application Model Parallel Training...

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Robotics, Control and Automation (ICRCA), international conference on

作者： Xuebo Zhang National Key Laboratory of Intelligent Spatial Information College of Aerospace Information Aerospace Engineering University Beijing China

ISBN: (数字)9798331544577

ISBN: (纸本)9798331544584

In response to the long training time of satellite remote sensing application models, this paper first introduces the main methods of parallel training, as well as the support provided by PyTorch for parallel training. Based on this, the target detection model YOLOv4 and the U-Net-based land-sea segmentation model were trained in parallel, and the experiments showed that the training time of both types of models was significantly reduced.

关键词： Training Satellites Automation Training data Object detection parallel processing Data models Remote sensing Robots

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Design of a Hybrid Encryption Scheme Based on Software and Hardware Collaboratin

Design of a Hybrid Encryption Scheme Based on Software and H...

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IEEE international conference on Signal and Image processing (ICSIP)

作者： Xuankai Liu Bing Li School of Integrated Circuit Southeast University China School of Cyber Science and Engineering Southeast University China

ISBN: (数字)9798350350920

ISBN: (纸本)9798350350937

With the rapid development of electronic information technology, data security issues are becoming increasingly serious. Traditional single cryptographic algorithms cannot meet the increasing demands of security and computational speed. In order to solve the problem of fast and secure transmission of large amounts of data by embedded devices, this paper proposes an improved hybrid encryption algorithm based on national encryption algorithms such as SM2 and SM4. In the implementation methods of algorithms in embedded devices, software hardware collaborative design balances software flexibility and hardware parallelism, which also improves system security and reduces development and maintenance costs. therefore, this article uses software hardware collaborative design methods to implement hybrid encryption algorithms. In addition, this article also optimizes the hardware of SM2 point multiplication, which can be used in devices with limited hardware resources. the experimental results show that under a 16MHz clock and using the elliptic curve recommended by SM2 on GF (2 257 ), the encryption speed is 4.04ms/time, the decryption speed is 2.96ms/time, and the number of point multiplication is 1685 times per second on Xilinx DDR200T FPGA.

关键词： Image processing Software algorithms Collaboration parallel processing Hardware Software Encryption

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Implementing Arbitrary/Common Concurrent Writes of CRCW PRAM 21

Implementing Arbitrary/Common Concurrent Writes of CRCW PRAM

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50th international conference on parallel processing (ICPP)

作者： Ghanim, Fady Elwasif, Wael R. Bernholdt, David E. Oak Ridge Natl Lab Oak Ridge TN 37830 USA

ISBN: (纸本)9781450384414

the parallel Random Access Machines (PRAM) abstraction is the simplest and most elegant algorithmic model for the design and analysis of parallel algorithms. It consists of different models categorized based on the underlying memory access mode used, the most powerful of which is the Concurrent Read Concurrent Write (CRCW) model. A PRAM algorithm describes a series of rounds, each of which consists of a collection of operations that can be executed concurrently within the same time step. However, the lack of support for concurrent memory accesses and the prevalence of asynchronous programming models led to the belief that implementing CRCW PRAM algorithms is unattainable and prompted many to avoid this model except for theoretical studies of optimal performance. In this work, we study the arbitrary and common concurrent writes in the CRCW PRAM model and explore implementation challenges on general-purpose systems. Moreover, we examine current practices for implementing common/arbitrary concurrent writes and propose a new efficient lightweight and thread-safe method to implement concurrent writes through leveraging atomic instructions. To demonstrate the efficacy of our method, we developed OpenMP kernels for classical CRCW PRAM algorithms and provide experimental results and comparisons based on run time performance measured over the x86 multicore architecture. Our results show a performance speedup compared to current practices up to 4.5x across all our benchmarks.

关键词： CRCW PRAM parallel algorithms Arbitrary Concurrent Writes Write-conflict resolution parallel architectures

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Two Partially Reconfigurable architectures For Efficient Implementation of Convolutional Neural Networks (CNNs

Two Partially Reconfigurable Architectures For Efficient Imp...

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international Engineering conference (IEC)

作者： Hakem Beitollahi

Today, convolutional neural networks (CNN) are widely used in many applications of artificial intelligence (AI), including image processing, video processing, natural language processing, and forecasting time series. CNNs require heavy computations to provide significant accuracy for many AI tasks. Normally, the training phase of CNNs is done through GPUs. However, the inference phase, which runs on the edge devices, is executed through a dedicated hardware accelerator. therefore, the efficient implementations of CNNs to improve performance using limited resources without accuracy reduction is a challenge for AI systems for edge devices. One of the architectures for the efficient execution of CNNs is the array-based accelerator that consists of an array of similar processing Elements (PEs). the array accelerators are popular as high-performance architecture using the features of parallel computing and data reuse. these accelerators are optimized for a set of CNN layers, not for individual layers. Using the same accelerator dimension size to compute all CNN layers with varying shapes and sizes leads to the resource underutilization problem. To handle this challenge, two research teams under my supervision propose two solutions namely CNNX and RASHT in last few years. In my talk, I will discuss both techniques and explain how we can have a flexible and scalable architecture for array-based accelerator that increases resource utilization. the RASHT architecture resizes PEs depending on the size and shapes of the layers. the CNNX implements a small and efficient accelerator and then using retiling executes the layers with different sizes and shapes. Both architectures have been evaluated through different CNN structures such as GoogLeNet, MobileNet and AlexNet. Experimental results show the effectiveness of both proposed hardware accelerators.

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Dynamic Compression and Knowledge Distillation on ViT Models Based on LoRA

Dynamic Compression and Knowledge Distillation on ViT Models...

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6th international conference on Intelligent Computing and Signal processing (ICSP)

作者： Tianyang Ling Jiale Wang School of electrical engineering and artificial intelligence Xiamen University Malaysia Sepang Malaysia School of computer science and engineering Nanyang Technological University Singapore

ISBN: (数字)9798350376548

ISBN: (纸本)9798350376555

In this work, we introduce an innovative approach to efficiently reduce the model size for transformer architectures. Our methodology includes low rank adaptation and knowledge distillation, leveraging a ViT-Base model as a teacher to guide a pruned version as the student. We show that our method can conduct a favourable tradeoff between model size and model accuracy.

关键词： Training Adaptation models Accuracy Computational modeling Computer architecture Signal processing Transformers Dynamic scheduling Resource management

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parallel Decoding of Trellis Stages for Low Latency Decoding of Tail-Biting Convolutional Codes

Parallel Decoding of Trellis Stages for Low Latency Decoding...

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international ITG conference on Source and Channel Coding (SCC)

作者： Amaael Antonini Wenhui Sui Zihan Qu Richard D. Wesel Department of Electrical and Computer Engineering University of California Los Angeles CA USA

ISBN: (数字)9798331522896

ISBN: (纸本)9798331522902

Convolutional codes are widely used in many applications. the encoders can be implemented with a simple circuit. Decoding is often accomplished by the Viterbi algorithm or the maximum a-posteriori decoder of Bahl et al. these algorithms are sequential in nature, requiring a decoding time proportional to the message length. For low latency applications this this latency might be problematic. this paper introduces a low latency decoder for tail-biting convolutional codes TBCCs that processes multiple trellis stages in parallel. the new decoder is designed for hardware with parallel processing capabilities. the overall decoding latency is proportional to the log of the message length. the new decoding architecture is modified into a list decoder, and the list decoding performance can be enhanced by exploiting linearity to expand the search space. Certain modifications to standard TBCCs are supported by the new architecture and improve frame error rate performance.

关键词： Convolutional codes Maximum a posteriori estimation Viterbi algorithm parallel processing Turbo codes Hardware parallel architectures Low latency communication Standards Maximum likelihood decoding

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