检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

2,722 篇 会议
57 册 图书
47 篇 期刊文献

馆藏范围

2,826 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,981 篇 工学
- 1,738 篇 计算机科学与技术...
- 845 篇 软件工程
- 308 篇 电气工程
- 248 篇 信息与通信工程
- 236 篇 电子科学与技术（可...
- 97 篇 控制科学与工程
- 65 篇 机械工程
- 48 篇 生物工程
- 47 篇 光学工程
- 37 篇 材料科学与工程（可...
- 37 篇 生物医学工程（可授...
- 35 篇 仪器科学与技术
- 27 篇 动力工程及工程热...
- 24 篇 建筑学
- 23 篇 化学工程与技术
- 22 篇 力学（可授工学、理...
- 22 篇 土木工程
569 篇 理学
- 403 篇 数学
- 123 篇 物理学
- 59 篇 生物学
- 50 篇 系统科学
- 40 篇 统计学（可授理学、...
- 31 篇 化学
229 篇 管理学
- 160 篇 管理科学与工程(可...
- 76 篇 图书情报与档案管...
- 65 篇 工商管理
52 篇 医学
- 42 篇 临床医学
25 篇 文学
- 18 篇 外国语言文学
23 篇 法学
- 23 篇 社会学
22 篇 经济学
- 22 篇 应用经济学
11 篇 农学
2 篇 教育学
2 篇 艺术学

主题

316 篇 parallel process...
203 篇 graphics process...
198 篇 computer archite...
144 篇 parallel archite...
107 篇 hardware
104 篇 parallel algorit...
94 篇 graphics process...
91 篇 parallel process...
81 篇 image processing
80 篇 algorithm design...
78 篇 computational mo...
74 篇 concurrent compu...
71 篇 signal processin...
71 篇 instruction sets
69 篇 parallel program...
65 篇 field programmab...
64 篇 parallel computi...
63 篇 gpu
58 篇 multicore proces...
57 篇 kernel

机构

10 篇 natl univ def te...
7 篇 inria rennes
6 篇 natl res nucl un...
6 篇 hosei univ dept ...
6 篇 lab efficient ar...
6 篇 southeast univ n...
6 篇 science and tech...
5 篇 univ aizu dept c...
5 篇 univ chinese aca...
5 篇 univ manchester ...
5 篇 city university ...
4 篇 tongji univ sch ...
4 篇 chinese acad sci...
4 篇 univ michigan ad...
4 篇 carleton univ sc...
4 篇 school of comput...
4 篇 faculty of infor...
4 篇 beijing inst tec...
4 篇 hainan internati...
4 篇 department of co...

作者

11 篇 dongarra jack
7 篇 jack dongarra
7 篇 liu jie
7 篇 zhang chuan
7 篇 quintana-orti en...
7 篇 kothapalli kisho...
6 篇 you xiaohu
6 篇 nakano koji
6 篇 peng shietung
6 篇 li yamin
6 篇 chu wanming
6 篇 wyrzykowski roma...
6 篇 griebler dalvan
5 篇 ito yasuaki
5 篇 liu xin
5 篇 wang guojun
5 篇 hannig frank
5 篇 geyong min
5 篇 wanlei zhou
5 篇 teich juergen

语言

2,763 篇 英文
38 篇 其他
23 篇 中文
2 篇 法文
1 篇 西班牙文
1 篇 葡萄牙文
1 篇 乌克兰文

检索条件"任意字段=9th International Conference on Algorithms and Architectures for Parallel Processing"

共 2826 条记录，以下是181-190 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

ORL-EPM: A Profit-Aware and Load-Driven Heterogeneous Resource Management Scheme with Collaborative Edge Computing 24th

ORL-EPM: A Profit-Aware and Load-Driven Heterogeneous Resou...

引用

24th international conference on algorithms and architectures for parallel processing, ICA3PP 2024

作者： Huang, Fengyi Zhang, Yutao Wang, Wenhua Guo, Jianxiong Xu, Yang Fan, Wentao Wang, Tian Hong Kong Baptist University Hong Kong China Hong Kong Baptist University United International College Beijing Normal University Zhuhai China Beijing Normal University Zhuhai China College of Computer Science and Electronic Engineering Hunan University Changsha China

ISBN: (纸本)9789819615414

To address the limitations of energy-efficient but computationally limited ARM64-based AI edge devices and general-purpose edge servers, this paper proposes a Decentralized Collaborative Heterogeneous Edge Computing (DCEC) architecture. this architecture combines edge servers with embedded AI devices to achieve low latency and enhanced computational capabilities. Commercially, the DCEC framework is divided into edge private clouds and edge public clouds, aiming to maximize the profits of Edge Service Providers (ESPs) through dynamic resource management. Considering task dynamism, complexity, and resource heterogeneity, this complex problem is formulated as a multi-stage mixed-integer nonlinear programming (MINLP) problem. We developed the ORL-EPM resource management framework—a three-layer optimization system that adjusts task scheduling based on varying latency sensitivity weights and heterogeneous resource demands. Additionally, we introduced a resource collaboration system based on resource leasing to manage resource overloads and accommodate diverse task complexities. this system includes three Economic Payment Models (EPMs) designed to achieve efficient and profitable resource utilization. Extensive simulation results indicate that this method ensures convergence and closely approximates optimal solutions across various scenarios, significantly outperforming existing methods. Testbed experiments demonstrate that the DCEC architecture can reduce latency by up to 21.83% in real-world applications, notably exceeding previous approaches. © the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Energy efficiency

来源：评论

学校读者我要写书评

暂无评论

Skywalker: Efficient Alias-method-based Graph Sampling and Random Walk on GPUs 30

Skywalker: Efficient Alias-method-based Graph Sampling and R...

引用

30th international conference on parallel architectures and Compilation Techniques (PACT)

作者： Wang, Pengyu Li, Chao Wang, Jing Wang, Taolei Zhang, Lu Leng, Jingwen Chen, Quan Guo, Minyi Shanghai Jiao Tong Univ Dept Comp Sci & Engn Shanghai Peoples R China Shanghai Qi Zhi Inst Shanghai Peoples R China

ISBN: (纸本)9781665442787

Graph sampling and random walk operations, capturing the structural properties of graphs, are playing an important role today as we cannot directly adopt computing-intensive algorithms on large-scale graphs. Existing system frameworks for these tasks are not only spatially and temporally inefficient, but many also lead to biased results. this paper presents Skywalker, a high-throughput, quality-preserving random walk and sampling framework based on GPUs. Skywalker makes three key contributions: first, it takes the first step to realize efficient biased sampling with the alias method on a GPU. Second, it introduces well-crafted load-balancing techniques to effectively utilize the massive parallelism of GPUs. third, it accelerates alias table construction and reduce the GPU memory requirement with efficient memory management scheme. We show that Skywalker greatly outperforms the state-of-the-art CPU-based and GPU-based baselines, in a wide spectrum of workload scenarios.

关键词： Graph sampling random walk graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

Potato Leaf Disease Detection: Comparative Study of the Performance of CNN architectures - VGG19, ResNet50 and DenseNet201

Potato Leaf Disease Detection: Comparative Study of the Perf...

引用

international conference of Signal processing and Intelligent Systems (ICSPIS)

作者： José Luis Ruíz Rodríguez Jonathan Moises Ruíz Rodríguez José María Pasco Sánchez Luis Antonio Orbegoso Moreno Isac Daniel Miñano Corro Edgar David Valverde Ramirez Department of Mechatronic Engineering National University of Trujillo Trujillo Peru Department of Agricultural Science National University of Trujillo Trujillo Peru Department of System Engineering National University of Trujillo Trujillo Peru

In this study, the performance of the CNN architectures VGG19, ResNet50, and DenseNet201 is compared in the detection of diseases in potato leaves. Within the scope of this research, the Plant Village database (2152 images) was employed. To this database composed of healthy potato leaves, late blight-infected leaves, and early blight-infected leaves, data augmentation with Gaussian Blur was applied, resulting in a total of 2760 images. the CNN architectures were trained using transfer learning with different batch sizes (16, 32, and 64). Based on three parameters, it was determined that the CNN architecture with the best performance was DenseNet201 with a batch size of 16, achieving an accuracy of 99.64%, requiring a storage capacity of 79.9 MB, and a training time of 16 minutes and 16 seconds.

关键词：

来源：评论

学校读者我要写书评

暂无评论

A Deep Learning framework and its Implementation for Diabetic Foot Ulcer Classification 9

A Deep Learning framework and its Implementation for Diabeti...

引用

9th IEEE international conference on Reliability, Infocom Technologies and Optimization (Trends and Future Directions), ICRITO 2021

作者： Prabhu, Madhava S Verma, Seema Banasthali University Electronics and Communication Engineering Rajasthan 304022 India

ISBN: (纸本)9781665417037

One of the major global healthcare issue is the Diabetes Mellitus (DM) and it is growing exponentially over the years. the complications that may arise in the diabetic patients is Diabetic Foot Ulcers (DFU) and if not treated on time, it may deteriorate the condition leading to the amputation. the pathogenic factors causing the superficial temperature changes in the foot can be effectively documented using infrared thermograph. the work discussed in this paper aims at proposing a model that can distinguish automatically the healthy skin versus the DFU class from the plantar thermos-grams using the deep learning algorithms. the proposed work is also implemented on a hardware platform using an Embedded Graphics processing Unit (GPU) called Jetson Nano that runs multiple neural networks simultaneously, the performance of the proposed work is compared and analysed with the existing algorithms such as DenseNet, VGGNet, and MatConvNet architectures. the results showed a significant improvement by achieving maximum accuracy of 97.9%. the deep learning framework to classify healthy and DFU class from plantar thermos-grams is also implemented using an Embedded GPU. the deployment of the proposed architecture using the NVIDIA Jetson Nano tool-kit highlights the appropriateness to embedded systems. this automated system is very useful in various healthcare scenarios to aid the clinicians to support their manual diagnosis of foot screening. © 2021 IEEE.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

Towards Automatic Block Size Tuning for Image processing algorithms on CUDA

Towards Automatic Block Size Tuning for Image Processing Alg...

引用

17th international conference on Software Technologies (ICSOFT)

作者： Guerfi, Imene Kriaa, Lobna Saidane, Leila Azouz Univ Manouba Natl Sch Comp Sci ENSI CRISTAL Lab RAMSIS Pole Manouba Tunisia

ISBN: (纸本)9789897585883

With the growing amount of data, computational power has became highly required in all fields. To satisfy these requirements, the use of GPUs seems to be the appropriate solution. But one of their major setbacks is their varying architectures making writing efficient parallel code very challenging, due to the necessity to master the GPU's low-level design. CUDA offers more flexibility for the programmer to exploit the GPU's power with ease. However, tuning the launch parameters of its kernels such as block size remains a daunting task. this parameter requires a deep understanding of the architecture and the execution model to be well-tuned. Particularly, in the Viola-Jones algorithm, the block size is an important factor that improves the execution time, but this optimization aspect is not well explored. this paper aims to offer the first steps toward automatically tuning the block size for any input without having a deep knowledge of the hardware architecture, which ensures the automatic portability of the performance over different GPUs architectures. the main idea is to define techniques on how to get the optimum block size to achieve the best performance. We pointed out the impact of using static block size for all input sizes on the overall performance. In light of the findings, we presented two dynamic approaches to select the best block size suitable to the input size. the first one is based on an empirical search;this approach provides the optimal performance;however, it is tough for the programmer, and its deployment is time-consuming. In order to overcome this issue, we proposed a second approach, which is a model that automatically selects a block size. Experimental results show that this model can improve the execution time by up to 2.5x over the static approach.

关键词： GPU Computing parallel Programming Program Optimization Auto-tuning and Face Detection

来源：评论

学校读者我要写书评

暂无评论

DRRA-based Reconfigurable Architecture for Mixed-Radix FFT

DRRA-based Reconfigurable Architecture for Mixed-Radix FFT

引用

international conference on VLSI Design

作者： Reeshita Kallapu Dimitrios Stathis Srinivas Boppu Ahmed Hemani School of Electrical Sciences Indian Institute of Technology Bhubaneswar (IITBBS) India Royal Institute of Technology (KTH) Sweden

Fast-Fourier Transform is an important algorithm which is used in digital signal processing and communication applications. Furthermore, mixed-radix FFT provides flexibility and increases the speed of FFT computation. For real-time processing, efficient hardware implementation using reconfigurable architectures is preferred which can offer higher performance and flexibility. In this paper, we propose an architecture for the implementation of the FFT that is derived from the Dynamically Reconfigurable Resource Array and has multiple parallel processing cells while also providing the flexibility to select the radix for each stage of the FFT. the twiddle factor generator proposed in this architecture minimizes the memory requirements and simplifies the hardware. Using the proposed architecture, various length FFTs were mapped onto either single cell or multiple cells in parallel. It is observed that the proposed architecture improves the performance by 2x times when compared to the existing FFT architectures.

关键词： Memory management Signal processing algorithms Computer architecture Transforms Switches Very large scale integration Hardware

来源：评论

学校读者我要写书评

暂无评论

iPUG for Multiple Graphcore IPUs: Optimizing Performance and Scalability of parallel Breadth-First Search 28

iPUG for Multiple Graphcore IPUs: Optimizing Performance and...

引用

28th Annual IEEE international conference on High Performance Computing, Data, and Analytics (HiPC)

作者： Burchard, Luk Cai, Xing Langguth, Johannes Simula Res Lab Oslo Norway Univ Oslo Oslo Norway BI Norwegian Business Sch Oslo Norway

ISBN: (纸本)9781665410168

parallel graph algorithms have become one of the principal applications of high-performance computing besides numerical simulations and machine learning workloads. However, due to their highly unstructured nature, graph algorithms remain extremely challenging for most parallel systems, with large gaps between observed performance and theoretical limits. Furthermore, most mainstream architectures rely heavily on single instruction multiple data (SIMD) processing for high floating-point rates, which is not beneficial for graph processing which instead requires high memory bandwidth, low memory latency, and efficient processing of unstructured data. On the other hand, we are currently observing an explosion of new hardware architectures, many of which are adapted to specific purposes and diverge from traditional designs. A notable example is the Graphcore Intelligence processing Unit (IPU), which is developed to meet the needs of upcoming machine intelligence applications. Its design eschews the traditional cache hierarchy, relying on SRAM as its main memory instead. the result is an extremely high-bandwidth, low-latency memory al the cost of capacity. In addition, the IPU consists of a large number of independent cores, allowing for true multiple instruction multiple data (MIMD) processing. Together, these features suggest that such a processor is well suited for graph processing. We test the limits of graph processing on multiple IPUs by implementing a low-level, high-performance code for breadth-first search (RFS), following the specifications of Graph500, the most widely used benchmark for parallel graph processing. Despite the simplicity of the BFS algorithm, implementing efficient parallel codes for it has proven to be a challenging task in the past. We show that our implementation scales well on a system with 8 IPUs and attains roughly twice the performance of an equal number of NVIDIA V100 GPUs using slate-of-the-art CUDA code.

关键词： BFS Graph500 IPU Performance Optimization

来源：评论

学校读者我要写书评

暂无评论

Efficient Approximate 8-Bit Binary parallel Subtractor Circuit: Design, Analysis, and Application in Negative Image Generation

Efficient Approximate 8-Bit Binary Parallel Subtractor Circu...

引用

international conference on Signal processing and Communication (ICSC)

作者： Sanjiv Kumar Gupta Amit Dhawan Manish Tiwari Sumit Kumar Jha Department of Electronics and Communication Engineering Motilal Nehru National Institute of Technology Allahabad Prayagraj Uttar Pradesh India

In the field of image processing and computer vision, negative imaging is vital for applications like medical imaging, art, and data enhancement. this paper introduces an efficient approach for negative image creation using an approximate 8-bit binary parallel subtractor (ABPS) circuit. the ABPS circuit reduces area usage by 33% and significantly cuts delay by 68.4% compared to conventional subtractor. the ABPS circuit balances precision and speed, making it ideal for tasks where small errors are acceptable. the efficacy of ABPS is demonstrated through its successful application in generating negative images, underscoring its performance.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Design and Implementation of FIR Filter Using Different architectures: A Comparative Study

Design and Implementation of FIR Filter Using Different Arch...

引用

international conference on Signal processing and Communication (ICSC)

作者： Teena Soni Anil Kumar Manoj Kumar Panda PDPM-IIITDM Jabalpur India

ISBN: (数字)9798331511890

ISBN: (纸本)9798331511906

the article proposes a hybrid sparse particle swarm optimization algorithm (HSPSO). this paper also presents an improved low-pass FIR filter design utilizing the HSPSO algorithm. the effectiveness of the proposed algorithm is contrasted with particle swarm optimization and sparse PSO in resolving the FIR filter design problem. HSPSO offered smaller best cost and execution time values. Furthermore, the suggested approach competes with the existing approaches in the literature, providing higher stopband attenuation values and smaller passband ripple values. the proposed work implemented the designed FIR filters, employing various multiplierless techniques, including the canonical signed digit (CSD) number system, fractional CSD (FCSD), distributed arithmetic (DA), and parallel distributed arithmetic (PDA). the comparative study of all the architectures and multiplier-based structure (MULT) is performed for the FPGA and ASIC environments. the DA outperforms all the architecture in area and power. the PDA with decomposition factor 4 provides the highest throughput and also smaller area and power compared with MULT, CSD, and FCSD-based architecture.

关键词： Costs Finite impulse response filters Signal processing algorithms throughput Attenuation Passband Particle swarm optimization Field programmable gate arrays Optimization Arithmetic

来源：评论

学校读者我要写书评

暂无评论

Workspace Analysis of an 8-UPS parallel Robot

Workspace Analysis of an 8-UPS Parallel Robot

引用

Robotics, Control and Automation (ICRCA), international conference on

作者： Feng GuoXin Xu Yong Chen Yuhao Li Huizi Zhang Yuhao Guo Shuyan Sun Weijun School of Mechanical and Automotive Engineering Shanghai University of Engineering Science Shanghai China

ISBN: (数字)9798331544577

ISBN: (纸本)9798331544584

To meet the production requirements of automated tasks in large-scale workspaces, a concept of an industrial robot designed for processing large components (such as wing riveting) and large workspaces is proposed, i.e. the 8-UPS parallel robot. the overall structure and branch configuration of the 8-UPS parallel robot are introduced. Using a three-dimensional search method, the workspace of the parallel mechanism under machining conditions is solved with MATLAB. the impact of rod length on the workspace is analyzed through attitude workspace studies.

关键词： parallel robots Automation Service robots Search methods Robot kinematics Production Machining Kinematics Industrial robots MATLAB

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共283页 << < 15 16 17 18 19 20 21 22 23 24 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：