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检索条件"任意字段=9th International Conference on Algorithms and Architectures for Parallel Processing"

共 2830 条记录，以下是221-230 订阅

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Novel Control Structures for parallel Two-Stage Converters Based on Shared SVPWAM/SVPWM

Novel Control Structures for Parallel Two-Stage Converters B...

引用

IEEE international conference on Power and Power and Renewable Energy (ICPRE)

作者： Zhuoqun Wu Dept. Electrical Engineering Yanshan University Qinhuangdao China

ISBN: (数字)9798350377460

ISBN: (纸本)9798350377477

Current-source converters are favored for their special and wide output voltage range. In order to increase power transmission, the structure and control strategies of parallel current-source converters have been developed. Meanwhile, two-stage cascaded current-source converters have an extremely wide output voltage range. However, until now, the control strategy for two-stage parallel current-source converters has not been studied. therefore, this paper focuses on the control structure of current-source converters with this particular topology. Based on the proposed control architecture, multiple parallel current-source converters only need to use the same SVPWM or SVPWAM (Space Vector Pulse Width Modulation) (Space Vector Pulse Width Amplitude Modulation), eliminating the need for each parallel converter to use its own modulation scheme as in traditional droop control architectures. Even in the presence of differences in parameters among paralleled branches and filters, sinusoidal grid current, unit power factor, IOOOV output for the load can still be achieved. Simulation results also validate the correctness of theoretical analysis and the effectiveness of the proposed approach.

关键词： Space vector pulse width modulation Multiplexing Reactive power Renewable energy sources Simulation Power transmission Microgrids Vectors Topology Voltage control

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Deep Learning Architecture with an Optimized Convolutional processing for the Segmentation of Retinal Blood Vessels

Deep Learning Architecture with an Optimized Convolutional P...

引用

international conference on Control, Decision and Information Technologies (CoDIT)

作者： Henda Boudegga Yaroub Elloumi Rostom Kachouri Asma Ben Abdallah Mohamed Hedi Bedoui Faculty of medicine Medical Technology and Image Processing Laboratory University of Monastir Tunisia ISITCom Hammam-Sousse University of Sousse Tunisia LIGM Univ Gustave Eiffel CNRS ESIEE Paris Marne-la-Vallée France

the retinal vascular tree (RVT) is crucial for the diagnosis of various ophthalmological diseases. Efficient segmentation of the RVT with reduced runtime is essential for clinical purposes. Recently, convolutional neural networks (CNNs) have been used for RVT segmentation. However, these architectures typically apply fixed and standard size of convolution kernels for all blocks, which may be unsuitable for accurately capturing vessel scales. In addition, these kernels are applied using 3D convolution layers across all channel depths, leading to higher computational complexity. In this work, we propose a novel deep learning architecture. the main contribution consists of performing a convolution processing where kernel size is chosen with respect to vessel scale variation, in order to enhance the quality of the segmentation of vascular trees. In addition, the convolution processing is insured through several layers with 2D kernels, to reduce the computational complexity. the proposed architecture is evaluated on DRIVE database reaching an average accuracy and sensitivity respectively in the order of 97.69 % and 91.69% in 0.75 second per fundus image.

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9th international conference on Statistical Language and Speech processing, SLSP 2021

9th International Conference on Statistical Language and Spe...

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9th international conference on Statistical Language and Speech processing, SLSP 2021

ISBN: (纸本)9783030895785

the proceedings contain 9 papers. the special focus in this conference is on Statistical Language and Speech processing. the topics include: Improving German Image Captions Using Machine Translation and Transfer Learning;Augmenting ASR for User-Generated Videos with Semi-supervised Training and Acoustic Model Adaptation for Spoken Content Retrieval;automatic News Article Generation from Legislative Proceedings: A Phenom-Based Approach;robustness of Named Entity Recognition: Case of Latvian;preface;invariant Representation Learning for Robust Far-Field Speaker Recognition;Various DNN-HMM architectures Used in Acoustic Modeling with Single-Speaker and Single-Channel.

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Arm Movements Recognition by Implementing CNN on Microcontrollers 9

Arm Movements Recognition by Implementing CNN on Microcontro...

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9th international conference on Control, Mechatronics and Automation (ICCMA)

作者： Qin, Siyu Zhang, Jiaqi Shen, Hongji Wang, Yizhou Univ Calif Irvine Irvine CA 92697 USA Univ Leeds Leeds LS2 9JT W Yorkshire England Xian Jiaotong Liverpool Univ Suzhou 215123 Peoples R China

ISBN: (纸本)9781665410731

Surface electromyography is a technique mainly used to detect hand movements to help patients regain control over their fingers or manipulate prosthetic arms. this body signal measuring technique is usually used with machine learning to recognize various arm movement s. However, past studies on arm movement recognitions used powerful computers that is inconvenient for patients to carry around to perform real-time sEMG signal measuring. this paper compares the performance of the two commonly used sEMG signal feature extraction methods, 1D-CNN, and 2D-CNN architectures. We first collected sEMG signals from 10 subjects. the 1D-CNN architecture reached an average recognition accuracy of 89.4% and the 2D-CNN architecture reached an average recognition accuracy of 98.9% the 2D-CNN architecture is converted from TensorFlow file to TensorFlow Lite file and is imported into the Arduino nano 33 BLE sense microcontroller. the microcontroller is able of repeating the machine learning process with a processing time of 79-85ms and 132-135ms respectively for 1D-CNN and 2D-CNN models. In the future, it is suggested that ASIC devices with specially designed electrodes can be applied to further reduce power consumption, size, and processing time of the device to help patients regain control of their hands or to manipulate prosthetic hands to perform dangerous experiments.

关键词： sEMG machine learning convolutional neural network TensorFlow lite

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A High-Speed Multiplier Design Using 2—Bit Reordering 4:3 Counter in a Wallace Tree Structure

A High-Speed Multiplier Design Using 2—Bit Reordering 4:3 C...

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international conference on Trends in Electronics and Informatics (ICEI)

作者： Saleem Syed Abdul Khader Khaderabad Sahithi Ankirapalli Swathi Lingamgunta Sasi Priyanka thammisetty Jaffar Ali Syed Dept. of Electronics and Communication Engineering Annamacharya Institute of Technology and Sciences Kadapa India

ISBN: (数字)9798331544607

ISBN: (纸本)9798331544614

It is known that the multiplier is widely applied, and to produce the outputs for the next stage, there is a reliance on the previous stage. Due to this, the multiplication process takes time to complete. As the binary bit counts of the multiplier and multiplicand increase, it takes longer to generate the output. this longer delay can severely impair the overall performance of digital systems, especially in applications requiring high-speed computations. therefore, optimizing the Multiplier for both speed and power efficiency is crucial to enhancing the performance of modern computing architectures. To achieve this optimization, various techniques such as parallel processing and reduced gate counts can be employed. Moreover, utilising advanced algorithms and hardware accelerators can enhance the efficiency of these multipliers in challenging computational settings. this will affect the circuit performance. A new technique known as the reordering technique is implemented in this project to enhance the multiplier in terms of speed and efficiency. this method is implemented by separating the high-state bits from the low-state bits using the reordering circuit, and then the separated bits are processed in the usual manner. this helps in the reduction of critical path latency, which benefits by enhancing the circuit's power consumption as less power is being released as heat or another form.

关键词： Micromechanical devices Power demand Logic gates parallel processing Market research Delays Table lookup Informatics Adders Optimization

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Introducing a Stream processing Framework for Assessing parallel Programming Interfaces 29

Introducing a Stream Processing Framework for Assessing Para...

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29th Euromicro international conference on parallel, Distributed and Network-Based processing (PDP)

作者： Garcia, Adriano Marques Griebler, Dalvan Fernandes, Luiz G. L. Schepke, Claudio Pontifical Catholic Univ Rio Grande do Sul PUCRS Sch Technol Porto Alegre RS Brazil Tres de Maio Maio Fac SETREM Lab Adv Res Cloud Comp LARCC Tres De Maio Brazil Fed Univ Pampa UNIPAMPA Alegrete Brazil

Stream processing applications are spread across different sectors of industry and people9;s daily lives. the increasing data we produce, such as audio, video, image, and text are demanding quickly and efficiently ... 详细信息

ISBN: (纸本)9781665414555

Stream processing applications are spread across different sectors of industry and people's daily lives. the increasing data we produce, such as audio, video, image, and text are demanding quickly and efficiently computation. It can be done through Stream parallelism, which is still a challenging task and most reserved for experts. We introduce a Stream processing framework for asse s s ing parallel Programming Interfaces (PPIs). Our framework targets multi-core architectures and C++ stream processing applications, providing an API that abstracts the details of the stream operators of these applications. therefore, users can easily identify all the basic operators and implement parallelism through different PPIs. In this paper, we present the proposed framework, implement three applications using its API, and show how it works, by using it to parallelize and evaluate the applications with the PPIs Intel TBB, FastFlow, and SPar. the performance results were consistent with the literature.

关键词： Benchmark Framework parallel Programming Stream processing

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Data Center Infrastructure in the Era of Generative Artificial Intelligence

Data Center Infrastructure in the Era of Generative Artifici...

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Innovative Research in Applied Science, Engineering and Technology (IRASET),conference on

作者： Antonio Cortés Castillo Departamento de Informática Universidad de Panamá Ciudad de Panamá Panamá

ISBN: (数字)9798331532970

ISBN: (纸本)9798331532987

Nowadays, Generative Artificial Intelligence (GenAI) is increasingly making inroads in Data Centers, helping to improve aspects related to latency and high speed. Data center-level network infrastructures require managing large volumes of data using high-speed protocols such as InfiniBand, as it allows low latency and parallel processing, as well as various applied switches at different network architecture levels. In this article, we examine those protocols at the data communication level that GenAI uses to optimize and guarantee data flow between nodes, as well as the design and reference of network architectures in the field of GenIA. On the other hand, the components of the GenAI networks used are analyzed. Similarly, a case study is proposed where the performance of the Graphic processing Units (GPUs) is analyzed based on the definition of a series of metrics such as memory access, memory bandwidth, throughput, energy consumption, temperature, and clock speed, and that through the simulation of neural networks specifically using the Radial Basic Function (RBF) and Multilayer Perceptron (MLP) algorithms, it helps to understand and analyze to what extent these metrics behave and generate possible solutions in the field of data centers.

关键词： Measurement Data centers Protocols Generative AI Optical switches Memory management Graphics processing units Bandwidth throughput Servers

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Designing a 3D parallel Memory-Aware Lattice Boltzmann Algorithm on Manycore Systems 27th

Designing a 3D Parallel Memory-Aware Lattice Boltzmann Algor...

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27th international European conference on parallel and Distributed Computing (Euro-Par)

作者： Fu, Yuankun Song, Fengguang Purdue Univ Indianapolis IN USA Indiana Univ Purdue Univ Indianapolis IN 46202 USA

ISBN: (纸本)9783030856656;9783030856649

Lattice Boltzmann method (LBM) is a promising approach to solving Computational Fluid Dynamics (CFD) problems, however, its nature of memory-boundness limits nearly all LBM algorithms' performance on modern computer architectures. this paper introduces novel sequential and parallel 3D memory-aware LBM algorithms to optimize its memory access performance. the introduced new algorithms combine the features of single-copy distribution, single sweep, swap algorithm, prism traversal, and merging two temporal time steps. We also design a parallel methodology to guarantee thread safety and reduce synchronizations in the parallel LBM algorithm. At last, we evaluate their performances on three high-end manycore systems and demonstrate that our new 3D memory-aware LBM algorithms outperform the state-of-the-art Palabos software (which realizes the Fuse Swap Prism LBM solver) by up to 89%.

关键词： Lattice Boltzmann method Memory-aware algorithms parallel numerical methods Manycore systems

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parallel Identification of Unique Sequences in Nuclear Structure Calculations 1

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14th international conference on parallel processing and Applied Mathematics, PPAM 2022

作者： Langr, Daniel Dytrych, Tomáš Faculty of Information Technology Czech Technical University in Prague Thákurova 9 Praha16000 Czech Republic Nuclear Physics Institute Czech Academy of Sciences Řež 130 Řež25068 Czech Republic Department of Physics and Astronomy Louisiana State University Baton RougeLA70803 United States

ISBN: (数字)9783031304453

ISBN: (纸本)9783031304446

Reducing the set of sequences into the set of sequences that are unique can save a lot of memory space in computer programs. We study this problem on the symmetry-adapted no-core shell model (SA-NCSM) nuclear structure calculations, where duplicated sequences of different kinds naturally emerge in the data of the basis of the Hilbert space physically relevant to a given nucleus. For a fast solution of this problem on multicore architectures, we propose and present a multithreaded algorithm suitable for high performance computing (HPC) environments. Furthermore, we provide an experimental evaluation of this algorithm and show that, in practice, it can significantly reduce the time required to identify unique sequences in a real-world application. © 2023, the Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Software architecture

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Assembly Line Balancing with Collaborative Robots Under Uncertainty of Human processing Times

Assembly Line Balancing with Collaborative Robots Under Unce...

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international conference on Control, Decision and Information Technologies (CoDIT)

作者： Ilhem Slama Taha Arbaoui Amir Nourmohammadi Masood Fathi LIST3N Université de Technologie de Troyes Troyes France Division of Intelligent Production Systems University of Skövde Skövde Sweden Division of Industrial Engineering and Management Uppsala University Uppsala Sweden

this paper studies the assembly line balancing problem with collaborative robots in light of recent efforts to implement collaborative robots in industrial production systems under random processing time. A stochastic version with uncertain human processing time is considered for the first time. the issue is defined by the potential for simultaneous human and robot task execution at the same workpiece, either in parallel or in collaboration. We provide stochastic mixed-integer programming based on Monte Carlo sampling approach for the balancing and scheduling of collaborative robot assembly lines for this novel issue type. In order to minimise the line cost including fixed workstation operating costs and resource costs caused by exceeding cycle time, the model determines both the placement of collaborative robots at stations and the distribution of work among humans and robots.

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