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检索条件"任意字段=9th International Conference on Algorithms and Architectures for Parallel Processing"

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Flexible performance debugging of parallel and distributed applications

Flexible performance debugging of parallel and distributed a...

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9th international Euro-Par conference on parallel processing, Euro-Par 2003

作者： de Kergommeaux, Jacques Chassin Guilloud, Cyril de Oliveira Stein, B. Laboratoire LSR-IMAG B.P. 72 St. Martin d’Hères Cedex38402 France Laboratoire ID-IMAG ENSIMAG Antenne de Montbonnot ZIRST 51 avenue Jean Kuntzmann Montbonnot Saint Martin38330 France Departamento de Eletrônica e Computação Universidade Federal de Santa Maria – RS Brazil

ISBN: (纸本)354040788X

the Pajé approach to help performance debugging of parallel and distributed applications is to provide behavioral visualizations of their program executions to programmers. this article describes how Pajé was designed to be usable for a variety of programming models. Trace recording and trace manipulation facilities can be generated from a description of the events to be traced. the visualization tool includes a trace-driven simulator reconstructing the behavior of the observed executions of the applications being debugged. the Pajé simulator is generic and can be specialized by the types of the objects to be visualized, the representation of these objects and their relations. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Application programs

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Demonstration of P-GRADE job-mode for the grid

Demonstration of P-GRADE job-mode for the grid

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9th international Euro-Par conference on parallel processing, Euro-Par 2003

作者： Kacsuk, P. Lovas, R. Kovács, J. Szalai, F. Gombás, G. Podhorszki, N. Horváth, Á. Horányi, A. Szeberényi, I. Delaitre, T. Terstyánszky, G. Gourgoulis, A. Hungarian Academy of Sciences P.O. Box 63 Budapest1518 Hungary Hungarian Meteorological Service P. O. Box 38 BudapestH-1525 Hungary Department of Control Engineering and Information Technology Budapest University of Technology and Economics Pázmány Péter sétány 1/D BudapestH-1117 Hungary Cavendish School of Computer Science University of Westminster 115 New Cavendish Street LondonW1W 6UW United Kingdom

ISBN: (纸本)354040788X

the P-GRADE job execution mode will be demonstrated on a small Grid containing 3 clusters from Budapest and London. the first demonstration illustrates the Grid execution of a parallel meteorology application. the parallel program will be on-line monitored remotely in the Grid and locally visualized on the submitting machine. the second demonstration will use a parallel traffic simulation program developed in P-GRADE to show the usage of the PGRADE job mode for Grid execution. the parallel program will be checkpointed and migrated to another cluster of the Grid. On-line job and execution monitoring will be demonstrated. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Demonstrations

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C-perfect hashing schemes for binary trees, with applications to parallel memories

C-perfect hashing schemes for binary trees, with application...

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9th international Euro-Par conference on parallel processing, Euro-Par 2003

作者： Cordasco, Gennaro Negro, Alberto Scarano, Vittorio Rosenberg, Arnold L. Dipartimento di Informatica ed Applicazioni 'R.M. Capocelli' Università di Salerno BaronissiSA84081 Italy Dept. of Computer Science University of Massachusetts Amherst AmherstMA01003 United States

ISBN: (纸本)354040788X

We study the problem of mapping tree-structured data to an ensemble of parallel memory *** are given a "conflict tolerance" c, and we seek the smallest ensemble that will allow us to store any nvertex rooted binary tree with no more than c tree-vertices stored on the same module. Our attack on this problem abstracts it to a search for the smallest c-perfect universal graph for complete binary trees. We construct such a graph which witnesses that only O ( c(1−1/c) · 2(n+1)/(c+1) ) memory modules are needed to obtain the required bound on conflicts, and we prove that Ω ( 2(n+1)/(c+1) ) memory modules are necessary. these bounds are tight to within constant factors when c is fixed—as it is with the motivating application. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Binary trees

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parallel linear system solution and its application to railway power network simulation

Parallel linear system solution and its application to railw...

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9th international Euro-Par conference on parallel processing, Euro-Par 2003

作者： Ercan, Muhammet F. Fung, Yu-Fai Ho, Tin-Kin Cheung, Wai-Leung School of Electrical and Electronic Eng Singapore Polytechnic Singapore Dept. of Electrical Eng The Hong Kong Polytechnic University Hong Kong

ISBN: (纸本)354040788X

the Streaming SIMD extension (SSE) is a special feature embedded in the Intel Pentium III and IV classes of microprocessors. It enables the execution of SIMD type operations to exploit data parallelism. this article presents improving computation performance of a railway network simulator by means of SSE. Voltage and current at various points of the supply system to an electrified railway line are crucial for design, daily operation and planning. With computer simulation, their time-variations can be attained by solving a matrix equation, whose size mainly depends upon the number of trains present in the system. A large coefficient matrix, as a result of congested railway line, inevitably leads to heavier computational demand and hence jeopardizes the simulation speed. With the special architectural features of the latest processors on PC platforms, significant speed-up in computations can be achieved. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Linear systems

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KOJAK - A tool set for automatic performance analysis of parallel programs

KOJAK - A tool set for automatic performance analysis of par...

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9th international Euro-Par conference on parallel processing

作者： Mohr, B Wolf, F Forschungszentrum Julich Zent Inst Angew Math D-52425 Julich Germany Univ Tennessee Dept Comp Sci Innovat Comp Lab Knoxville TN 37996 USA

Today9;s parallel computers with SMP nodes provide both multithreading and message passing as their modes of parallel execution. As a consequence, performance analysis and optimization becomes more difficult and cr... 详细信息

ISBN: (纸本)354040788X

Today's parallel computers with SMP nodes provide both multithreading and message passing as their modes of parallel execution. As a consequence, performance analysis and optimization becomes more difficult and creates a need for advanced performance tools that are custom made for this class of computing environments. Current state-of-the-art tools provide valuable assistance in analyzing the performance of MPI and OpenMP programs by visualizing the run-time behavior and calculating statistics over the performance data. However, the developer of parallel programs is still required to filter out relevant parts from a huge amount of low-level information shown in numerous displays and map that information onto program abstractions without tool support. the KOJAK project (Kit for Objective Judgement and Knowledge-based Detection of Performance Bottlenecks) is aiming at the development of a generic automatic performance analysis environment for parallel programs. Performance problems are specified in terms of execution patterns that represent situations of inefficient behavior. these patterns are input for an analysis process that recognizes and quantifies the inefficient behavior in event traces. Mechanisms that hide the complex relationships within event pattern specifications allow a simple description of complex inefficient behavior on a high level of abstraction. the analysis process transforms the event traces into a three-dimensional representation of performance behavior. the first dimension is the kind of behavior. the second dimension describes the behavior's source-code location and the execution phase during which it occurs. Finally, the third dimension gives information on the distribution of performance losses across different processes or threads. the hierarchical organization of each dimension enables the investigation of performance behavior on varying levels of granularity. Each point of the representation is uniformly mapped onto the corresponding fra

关键词： Message passing

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On utilizing experiment data repository for performance analysis of parallel applications

On utilizing experiment data repository for performance anal...

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9th international Euro-Par conference on parallel processing, Euro-Par 2003

作者： Truong, Hong-Linh Fahringer, thomas Institute for Software Science University of Vienna Liechtensteinstr. 22 ViennaA-1090 Austria

ISBN: (纸本)354040788X

Performance data usually must be archived for various performance analysis and optimization tasks such as multi-experiment analysis, performance comparison, automated performance diagnosis. However, little effort has been done to employ data repositories to organize and store performance data. this lack of systematic organization of data has hindered several aspects of performance analysis tools such as performance comparison, performance data sharing and tools integration. In this paper we describe our approach to exploit a relational-based experiment data repository in SCALEA which is a performance instrumentation, measurement, analysis and visualization tool for parallel programs. We present the design and use of SCALEA’s experiment data repository which is employed to store information about performance experiments including application, source code, machine information and performance data. Performance results are associated with experiments, source code and machine information. SCALEA is able to offer search and filter capabilities, to support multi-experiment analysis as well as to provide well-defined interfaces for accessing the data repository and leveraging the performance data sharing and tools integration. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Data integration

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Counteracting bank misprediction in sliced first-level caches

Counteracting bank misprediction in sliced first-level cache...

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9th international Euro-Par conference on parallel processing, Euro-Par 2003

作者： Torres, Enrique F. Ibañez, P. Viñals, V. Llabería, J.M. DIIS Universidad de Zaragoza Spain DAC Universidad Polit´ecnica de Catalunya Spain

ISBN: (纸本)354040788X

Future processors having sliced memory pipelines will rely on bank prediction to schedule memory instructions to a first-level cache split into banks. In a deeply pipelined processor, even a small bank misprediction rate may degrade performance severely. the goal of this paper is to counteract the bank misprediction penalty, so that in spite of such bank misprediction, performance suffers little. Our contribution is twofold: a new recovery scheme for latency misprediction, and two policies for selectively replicating loads to all banks. the proposals have been evaluated for 4 and 8-way superscalar processors and a wide range of pipeline depths. the best combination of our mechanisms improves IPC of an 8-way baseline processor up to 11%, removing up to two thirds of the bank misprediction penalty. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Pipeline processing systems

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Design of B(x)/sup -1/mod F(x) for high-speed communications

Design of B(x)/sup -1/mod F(x) for high-speed communications

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Asia-Pacific conference on Communications

作者： Sungsoo Choi Kwan-Ho Kim Kiseon Kim Power Telecommunication Network Research Group Korea Electrotechnology Research Institute Euiwang South Korea Department Information and Communication Engineering Gwangju Institute of Science and Technology Gwangju South Korea

ISBN: (纸本)0780381149

In designing high-speed communications, the smallest functional unit like arithmetic, B(x)/sup -1/mod F(x), should be carefully designed and optimized well to improve the overall performance. To do this, we study two variations that is, square-first and multiply-first type operations - for the repetition-operation of the numerical formula, AB/sup 2/. From these two variations, we propose m-bit parallel semi-systolic architectures for GF(2/sup m/) inversion. When we compared performance of them with those of different inversion architectures based on a normal power-sum operation, based on small grain of special power-sum operation, and based on a Euclidean algorithm, performance of the proposed one, which is based on small grain of special power-sum operation, is the best for the purpose of high-speed applications. When we implement a simplified 8-bit parallel semi-systolic architecture for square-first inversion circuit over GF(2/sup m/) by using 0.25 /spl mu/W CMOS library, it has 2495 equivalent logic-gates, 1848 1-bit latches, and the latency is 56 and the clock-rate is up to 580 MHz at 100% throughput.

关键词： Polynomials Circuits Galois fields Clocks Standards development Pipeline processing parallel architectures

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Implementation of a highly scalable architecture for fast inversion of triangular matrices

Implementation of a highly scalable architecture for fast in...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： F. Edman V. Owall Department of Electroscience Lund University Sweden

In this paper, an FPGA implementation of a novel and highly scalable hardware architecture for fast inversion of triangular matrices is presented. An integral part of modem signal processing and communications applications involves manipulation of large matrices. therefore, scalable and flexible hardware architectures are increasingly sought for. In this paper, the traditional triangular shaped array architecture with n(n+l)/2 communicating processors, with n being the number of inputs, is mapped to a linear structure with only n processors. the linear and the triangular shaped architectures are compared in aspect of area consumption, latencies, and maximum clocking speed. this paper also show that the linear array structure avoids drawbacks such as non-scalability, large area, and large power consumption. the implementation is based on a numerically stable recurrence algorithm, which has excellent properties for hardware implementation.

关键词： Signal processing algorithms Hardware Clocks Array signal processing Energy consumption parallel processing Computer architecture Modems Delay throughput

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A fast parallel Reed-Solomon decoder on a reconfigurable architecture 03

A fast parallel Reed-Solomon decoder on a reconfigurable arc...

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international conference on Hardware/Software Codesign and System Synthesis (CODES)

作者： A. Koohi Nader Bagherzadeh Chengzi Pan EECS Department University of California Irvine USA

ISBN: (纸本)9781581137422

this paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targeting on streamed applications such as multimedia and DSP. Numerous modifications of the first-generation of the architecture have made a scalable computation and communication intensive architecture capable of extracting parallelisms of fine grain in instruction level. Many algorithms and the whole digital video broadcasting base-band receiver as well, have been mapped onto the second architecture with impressive performance. the mapping of a Reed-Solomon decoder proposed in the paper highly parallelizes all of its sub-algorithms, including Syndrome Computation, Berlekamp Algorithm, Chein Search, and Error Value Computation, in a SIMD fashion. the mapping is tested on a cycle-accurate simulator, "Mulate", and the performance is encouragingly better than other architectures. the decoding speed of the RS (255,239,16) decoder using two different methods of GF multiplication can be 1.319 Gbps and 2.534 Gbps, respectively. Furthermore, since there is no functionality specifically tailored to Reed-Solomon decoder, the result has demonstrated the capability of MorphoSys architecture to extracting instruction level parallelism from streamed applications.

关键词： Reed-Solomon codes Decoding Reconfigurable architectures Concurrent computing Computer architecture Streaming media parallel processing Application software Digital signal processing Computer aided instruction

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