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9th international conference on parallel and Distributed Systems (ICPADS 2002)

作者： Wang, JH Tsutaya, Y Segawa, N Yamane, S Murayama, Y Miyazaki, M Suzuki, H Iwate Prefectural Univ Fac Software & Informat Sci Takizawa Iwate 0200193 Japan

ISBN: (纸本)0769517609

Using a cluster of PCs or workstations or the likes (called nodes) to implement the database server can bring us two great benefits: high scalability and parallel processing capability Before such a database server can be put into actual use, however two problems have to be solved. the one is how we cope with the data-skew since it can degrade the system performance significantly. the other is how a node is connected to or disconnected from a database server without affecting the users. One general solution to both problems is to redistribute the data. Unfortunately, this would take the data off line for a long time. In fact, numerous applications such as that for reservations, finance, process control, hospitals, police, and armed forces cannot afford the off-line data for any significant amount of time. In this paper we address the subject of balancing data load on line, i.e., balancing data load concurrently with users' reading and writing of the database. Main contributions are an effective approach for this purpose and a comprehensive performance study of the possible alternatives.

关键词： Databases Degradation Finance Hospitals parallel processing Personal communication networks Process control Scalability System performance Workstations

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Compiler-controlled parallelism-independent scheduling for parallel and distributed system 6th

Compiler-controlled parallelism-independent scheduling for p...

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6th international conference on Applied parallel Computing, PARA 2002

作者： Nikolova, Kirilka You, Sou Pei Sowa, Masahiro University of Electro-Communications Chofugaoka-1-5-1 Tokyo182-8585 Japan

ISBN: (纸本)354043786X

the objective of the parallelism-independent (PI) scheduling is minimization of the completion time of a parallel application for any number of processing elements in the computing system. We propose several parallelism-independent algorithms which are either applicable for distributed computing systems, i.e. systems of autonomous processors connected via communication links (in this case we provide explicit message communication scheduling) or for tightly coupled multiprocessor systems or architectures exploiting instruction level parallelism as well. the algorithms are hybrid but predominantly done at compile time in order to reduce the dynamic overhead and scheduling hardware. All the traditional static scheduling algorithms produce machine codes with fixed degree of parallelism which cannot be executed efficiently on computer systems with different degrees of parallelism. Our algorithms eliminate this problem closely related to the distribution of parallel programs. © Springer-Verlag Berlin Heidelberg 2002.

关键词： Scheduling

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High performance parallel multiplier using Wallace-Booth algorithm

High performance parallel multiplier using Wallace-Booth alg...

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IEEE international conference on Semiconductor Electronics (ICSE)

作者： Lakshmanan Othman, M Ali, MAM Univ Kebangsaan Malaysia Dept Elect Elect & Syst Engn Signal Proc Res Grp Bangi 43600 Selangor DE Malaysia

ISBN: (纸本)0780375785

this paper presents an efficient implementation of a VLSI high speed parallel multiplier using the Radix_4 modified Booth algorithm and the Wallace Tree structure the design is structured for a n x in multiplication where n can reach up to 126 bits. the Wallace Tree structure serves to compress the partial product term by a ratio of 3:2 111 To enhance the speed of operation, carry-look-ahead(CLA) adders are used which is independent on the number of bits of the two operands[2]. An efficient VHDL code was written and successfully simulated and synthesised using Altera's MaxplusII(10.0) and ModelSim3.4 CAD tools.

关键词： Signal processing algorithms Tree data structures Digital signal processing chips Algorithm design and analysis Logic arrays Design engineering Systems engineering and theory Very large scale integration Signal design Adders

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A duality theorem for two connectivity-preserving parallel shrinking transformations

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FUTURE GENERATION COMPUTER SYSTEMS 2002年第7期18卷 931-937页

作者： Umeo, H Mauri, G Osaka Electrocommun Univ Grad Sch Engn Fac Informat Sci & Technol Dept Informat Engn Neyagawa Osaka 5728530 Japan Univ Milano Bicocca Dipartimento Informat Sistemat & Comun I-20126 Milan Italy

We study two classical connectivity-preserving parallel shrinking algorithms proposed to recognize and label two-dimensional connected components of binary images. the algorithms we consider were developed by Beyer [Recognition of topological invariants by iterative arrays, Ph.D. thesis, MIT, 1969, p. 144] and Levialdi [Commun. ACM 15 (1) (1972) 7] independently for the purpose of shrinking 4-connected and 8-connected components of binary images in linear time, respectively. It is shown that those two independently developed algorithms are closely related and in a sense they are in a dual relation such that, for any initially given binary image and its inverted one, one algorithm produces, simultaneously, an image which is dual of the one produced by the other, step-by-step. (C) 2002 Elsevier Science B.V. All rights reserved.

关键词： binary image processing connectivity-preserving parallel shrinking algorithm connectivity recognition labeling problem cellular automaton

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processing time saving in low power voice coding applications using synchronous reconfigurable co-processing architecture

Processing time saving in low power voice coding application...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： S.M. Carta L. Raffo Department of Electrical and Electronic Engineering University of Cagliari Cagliari Italy

Power dissipation reduction is a stringent constraint in modern mobile devices. It can be obtained by supply voltage or frequency reduction, but a strong reduction of number of cycles for operation must be achieved. To this end, reconfigurable architectures are a valuable solution. In this paper a reconfigurable architecture is designed and successfully tested on GSM coding. An average reduction of 98.2% cycles for specific tasks and of 44.6% cycles for overall computation with respect to standard general purpose processors is obtained.

关键词： Coprocessors Kernel Frequency Signal processing algorithms Power dissipation Voltage Reconfigurable architectures Computer architecture Capacitance Partitioning algorithms

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Recursive filters using systolic architectures and switched capacitor techniques

Recursive filters using systolic architectures and switched ...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： D. Chikouche R.E. Bekka A. Boucenna Département d Electronique Faculté des Sciences de IIngénieur Université de Satif Setif Algeria

In this paper, the discrete state space recursive filters are implemented in the form of parallel array processors. the state space description permits the straightforward application of systolic architectures to realize recursive filters of 1D and 2D types. We show that the recursivity inherent to the filtering algorithm introduces a latency proportional to the filter order. Moreover, we show that the use of the CTP decomposition technique together with the cylindrical-type structures reduces significantly this latency and improves the computation throughput of these arrays. the processing cells of the systolic array are designed via switched-capacitor techniques.

关键词： Filters Capacitors State-space methods Computer architecture throughput Equations Filtering algorithms Delay Systolic arrays Process design

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parallelisation of the 1-D block filter algorithm to run on multiple DSPs

Parallelisation of the 1-D block filter algorithm to run on ...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： M. Aziz S. Boussakta D.C. McLernon Institute of Integrated Information Systems School of Electronic and Electrical Engineering University of Leeds Leeds UK

parallel processing is a vital tool for many scientific and industrial applications where real time constraints apply; in many applications the use of parallel processing and multiprocessor platforms seems to be the favourable solution for achieving acceptable throughput. Hence parallel processing algorithms are vital tools to achieve a good trade off between hardware cost, system efficiency and power. In this paper, the one-dimensional generalised parallel block filter algorithm based on the overlap-add approach is implemented on multi-DSPs platform. the mathematical concept of the input stage, output stage and the generalised direct filter equation are given. Also the 1-D parallel algorithm is shown and a suitable parallel architecture is presented.

关键词： Digital signal processing Finite impulse response filter Equations Filtering Signal processing algorithms parallel processing parallel algorithms Digital filters Information systems Industrial electronics

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A parallel divide-and-conquer scheme for Delaunay triangulation 9

A parallel divide-and-conquer scheme for Delaunay triangulat...

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9th international conference on parallel and Distributed Systems, ICPADS 2002

作者： Chen, Min-Bin Chuang, Tyng-Ruey Wu, Jan-Jan Department of Management Information Systems Chung Kuo Institute of Technology Wenshan Taipei 116 Taiwan Institute of Information Science Academia Sinica Nankang Taipei 115 Taiwan

ISBN: (纸本)0769517609

this paper describes a parallel divide-and-conquer-algorithm for Delaunay triangulation. this algorithm finds the affected zone that cover the triangulations that may be modified during the merge of two sub-block triangulations. With the aid of the affected zone, communications between processors are reduced, the time complexity of divide-and-conquer remains O(n log n), and the affected zone can be found in O(n) time steps, where n is the number of points. the code was implemented with C, FORTRAN and MPI, so it was easy to port this program to other machines. Experimental results on IBM SP2 show that a parallel efficiency of 34%-96% for general distributions can be achieved on an 16-node distributed memory system. © 2002 IEEE.

关键词： Finite element method

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Mathematical modelling of ground penetrating radar: parallel computing applications

Mathematical modelling of ground penetrating radar: Parallel...

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9th international conference on Ground Penetrating Radar (GPR 2002)

作者： Cassidy, NJ Tuckwell, GW Univ Keele Sch Earth Sci & Geog Keele ST5 5BG Staffs England

ISBN: (纸本)0819445223

In heterogeneous sub-surface environments, the evaluation of GPR sections is complicated by the influence of near-field effects, antenna radiation patterns, velocity variations and surveying inconsistencies. Section interpretation can be exceedingly difficult, even with advanced processing methods, and therefore mathematical modelling has become an increasingly popular addition to traditional techniques. the Finite-Difference Time-Domain method (FDTD) is the most common, but to be of practical use the modelling scheme must incorporate realistic antenna configurations, complex sub-surface geometries and accurate material property descriptions. these additional components add computational complexity to the models and, at present, most single processor FDTD schemes are only capable of modelling relatively basic three-dimensional data sets in practical time scales. Modem parallel computing techniques have the potential to overcome these limitations by spreading the computational demand across a number of processors (or individual PC's). these PC 'cluster' machines provide the necessary computational power required to model more complex GPR problems in realistic time-scales. Consequently, the scope and run-time of current GPR FDTD modelling applications can be improved making them an accessible and affordable aid to GPR interpretation.

关键词： parallel modelling finite-difference processing interpretation

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Fast line detection using major line removal morphological Hough transform

Fast line detection using major line removal morphological H...

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international conference on Neural Information processing

作者： Leo Chin Sim H. Schroder G. Leedham Centre for High Performance Embedded Systems Nanyang Technological University Republic of Singapore School of Computer and Information Technology Royal Melbourne Institute of Technology Australia

this paper describes an implementation of a novel line removal Hough transform on a new parallel architectural system, referred to as a hybrid system. the algorithm, which is used for detecting lines in an image, strips away major line so that minor lines can be more easily detectable. the algorithm was subsequently implemented on the hybrid system. A hybrid system is a combination of SIMD and MIMD system processing the data in parallel. In this paper, we also introduce a new SIMD concept.

关键词： Concurrent computing Pattern recognition Voting Personal communication networks Message passing Shape Taxonomy parallel architectures Systolic arrays Embedded system

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