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检索条件"任意字段=9th International Conference on Algorithms and Architectures for Parallel Processing"

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Accelerate the calculation of NURBS curves and surfaces based on parallel architecture 9

Accelerate the calculation of NURBS curves and surfaces base...

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9th international conference on parallel and Distributed Systems, ICPADS 2002

作者： Ou, Shih-Ching Shiu, Li-Hong Hsiao, Sung-Jung Sung, Wen-Tsai Automation and CAD Lab. Department of Electrical Engineering National Central University Taiwan Department of Computer Science and Information Engineering National Central University Taiwan

ISBN: (纸本)0769517609

the aim of the paper is to propose a three-dimensional graphics chip with parallel architecture, in accordance with the chip of the NURBS algorithm was structured. this architecture presents a regular and easily scalable structure, suitable for VLSI implementation, which can be efficiently exploited for the computing process. this architecture can apply to a peripheral device of a computer and a user can use it for fitting curves and surfaces, convert NURBS curves to Bezier and so on, which have 16 bit precision. In this paper, we first describe the framework of the whole system. Secondly, we introduce the hardware of FPGA and explain the principle. Next, we will also illustrate NURBS, and test and verify using Visual C++ and OpenGL. the performance of the proposed architecture is improved by the use of carry save arithmetic which permits the reduction of the system time cycle. © 2002 IEEE.

关键词： Application programming interfaces (API)

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A novel division algorithm for parallel and sequential processing

A novel division algorithm for parallel and sequential proce...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： K. Tatas D.J. Soudris D. Siomos M. Dasygenis A. thanailakis VLSI Design and Testing Center Department of Electrical & Computer Engineering Democritus University of Thrace Xanthi Greece

A new algorithm for reducing the division operation to a series of smaller divisions is introduced. Partitioning the dividend into segments, we perform divisions, shifts, and accumulations taking into account the weight of dividend bits. Each partial division can be performed by any existing division algorithm. From an algorithmic point of view, computational complexity analysis is performed in comparison with existing algorithms. From an implementation point of view, since the division can be performed by any existing divider, the designer can chose the divider which meets his specifications best. Two possible implementations of the algorithm, namely the sequential and parallel are derived, with several variations, allowing performance, cost, and cost/performance trade-offs.

关键词： Signal processing algorithms Partitioning algorithms Costs Iterative algorithms Algorithm design and analysis Computational complexity Performance analysis Delay Power system restoration Digital signal processing

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An artificial neural network guided parallel genetic approach to the routing problem for field programmable gate arrays

An artificial neural network guided parallel genetic approac...

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international conference on Neural Information processing

作者： A. Muthukaruppan S. Suresh B.S.N. Rao V. Kamakoti Digital Circuits and VLSI Laboratory Department of Computer Science and Engineering Indian Institute of Technology Chennai India

this paper introduces the concept of "artificially intelligent parallel genetic algorithms", in the form of an artificial neural network, to provide a solution for the routing problem for FPGAs.

ISBN: (纸本)9810475241

this paper introduces the concept of "artificially intelligent parallel genetic algorithms", in the form of an artificial neural network, to provide a solution for the routing problem for FPGAs.

关键词： Artificial neural networks Genetics Routing Field programmable gate arrays Switches Delay Logic arrays Digital circuits Very large scale integration Laboratories

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A full adder based methodology for scaling operation in residue number system

A full adder based methodology for scaling operation in resi...

引用

IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： D. Soudris M. Dasygenis K. Mitroglou K. Tatas A. thanailakis Department of Electrical and Computer Engineering Democritus University of Thrace Xanthi Greece

A systematic methodology for designing full-adder-based architectures in residue number system for scaling operation and its software tool development, are introduced. Starting from the mathematical description of scaling operation in RNS, we end up with the VHDL description of a full-adder based architecture. the proposed tool was implemented in C++ language and it is available for PC and HP platforms. the derived architectures are characterized by smaller hardware complexity and higher throughput rates than existing ones.

关键词： Digital signal processing Computer architecture Hardware throughput Very high speed integrated circuits Design methodology Real time systems parallel processing Dynamic range Adders

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A duality theorem for two connectivity-preserving parallel shrinking transformations

A duality theorem for two connectivity-preserving parallel s...

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4th international conference on Cellular Automata for Research and Industry (ACRI 2000)

作者： Umeo, H Mauri, G Osaka Electrocommun Univ Grad Sch Engn Fac Informat Sci & Technol Dept Informat Engn Neyagawa Osaka 5728530 Japan Univ Milano Bicocca Dipartimento Informat Sistemat & Comun I-20126 Milan Italy

We study two classical connectivity-preserving parallel shrinking algorithms proposed to recognize and label two-dimensional connected components of binary images. the algorithms we consider were developed by Beyer [Recognition of topological invariants by iterative arrays, Ph.D. thesis, MIT, 1969, p. 144] and Levialdi [Commun. ACM 15 (1) (1972) 7] independently for the purpose of shrinking 4-connected and 8-connected components of binary images in linear time, respectively. It is shown that those two independently developed algorithms are closely related and in a sense they are in a dual relation such that, for any initially given binary image and its inverted one, one algorithm produces, simultaneously, an image which is dual of the one produced by the other, step-by-step. (C) 2002 Elsevier Science B.V. All rights reserved.

关键词： binary image processing connectivity-preserving parallel shrinking algorithm connectivity recognition labeling problem cellular automaton

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th-CluFS: an open platform cluster file system

TH-CluFS: an open platform cluster file system

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IEEE international conference on algorithms and architectures for parallel processing (ICAP)

作者： Qifeng Huang Weimin Zheng Meiming Shen Department of Computer Science and Technology Tsinghua University Beijing China

ISBN: (纸本)0769515126

In this paper, we present the design and implementation of a new cluster file system, th-CluFS, which is based on the standard NFS protocol and is implemented in the user level space completely. this open platform file system is important as the clusters become larger and heterogeneous. To take advantages of the accumulated resources and high-speed network in clusters, th-CluFS follows a serverless architecture, hybrid distributed metadata management, and file granular data distribution, and it uses distributed metadata cache and unique cache to optimize performance. For the flexibility of th-CluFS, we plan to employ file migration to balance I/O load across nodes dynamically. According to the experiment results, we conclude that th-CluFS can meet the requirements of consistent file system view, performance and scalability gracefully.

关键词： File systems Load management Scalability Space technology High-speed networks Computer networks Concurrent computing High performance computing Kernel Computer science

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Neural network methods for radar processing

Neural network methods for radar processing

引用

international conference on Neural Information processing

作者： A.L. Tatuzov Russian Department of Defence Central Science Research Institute Russia

there are significant difficulties in radar automatic data processing arising from poor flexibility of known algorithms and low computational capacity of traditional computer devices. Neural networks can help the radar designer to overcome these difficulties as a result of computational power of neural parallel hardware and adaptive capabilities of neural algorithms. the idea of neural net application in the most difficult radar problems is proposed and analyzed. Some examples of neural methods for radar information processing are proposed and discussed: phase array antenna weights adaptation, genetic algorithms for optimization of multibased coded signals, data associations in multitarget environment, neural training for decision making systems. Results of the analysis for proposed methods prove that a considerable increase in efficiency can be achieved when neural networks are used for radar information processing problems.

关键词： Neural networks Radar antennas Information processing Adaptive arrays Phased arrays Data processing Algorithm design and analysis Computer networks Concurrent computing Neural network hardware

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Low-power high-order band-pass active-RC allpole filters using a "lossy" LP-BP transformation

Low-power high-order band-pass active-RC allpole filters usi...

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9th IEEE international conference on Electronics, Circuits and Systems, ICECS 2002

作者： Jurištć, Dražen Mijat, Neven Moschytz, George S. University of Zagreb Department of Electronic Systems and Information Processing Unska 3 HR-10000 Zagreb Croatia Sternwartstrasse 7 CH-8092 Zürich Switzerland

ISBN: (纸本)0780375963

the design procedure for high-order single amplifier BP filters is presented. A method for the design of 2nd- and 4th-order band-pass (BP) active-RC filters using a modified low-pass to band-pass (LP-BP) frequency transformation, was already presented in previous works [1],[2]. It was shown that a BP filter could be realized simply by the substitution of resistors and capacitors of the ladder in a low-pass (LP) prototype filter, by serial and parallel RC circuits. Such a substitution results from a so-called, "lossy" LP-BP transformation. In this paper, the design procedure is extended to higher-order BP filters, such as 6th- and 8 th-order. the design procedure is simple, and the closed-form design equations, are presented. Furthermore, it is shown that "impedance tapering" decreases sensitivities to component tolerances for the LP prototype, as well as for the resulting BP filter. the Schoeffler's sensitivity measure is used for the sensitivity analysis. © 2002 IEEE.

关键词： Bandpass filters

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parallel external selection algorithm on distributed memory systems

Parallel external selection algorithm on distributed memory ...

引用

IEEE international conference on algorithms and architectures for parallel processing (ICAP)

作者： Cheng Zhong Guoliang Chen Chao Yan Department of Computer Science University of Science and Technology Hefei China School of Computer and Information Engineering Guangxi University Nanning China

ISBN: (纸本)0769515126

the external selection problem is to select the record with the K-th smallest key from the given N records that are distributed and stored evenly on the D disks for the parallel machine with D processors. Each processor has its own primary memory of size M records and one disk, where N/D>M. the processors are connected with a /spl radic/D /spl times/ /spl radic/D mesh architecture. Based on a two-stage approach, this paper presents an efficient parallel external selection algorithm for the distributed-memory parallel systems. First, all the processors execute local external sorting in parallel, each processor sorts the N/D records on its own disk. Next, they execute parallel external selection from the D sorted sub-files on the D disks. this algorithm is asymptotically optimal and has a small constant factor of time complexity.

关键词： Sorting parallel machines Algorithm design and analysis Chaos Computer science parallel algorithms Internet Databases Artificial intelligence Statistics

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Pipeline architecture for two-dimensional discrete cosine transform and its inverse

Pipeline architecture for two-dimensional discrete cosine tr...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： J. Takala J. Nikara K. Punkka Institute of Digital and Computer Systems Tampere University of Technology Tampere Finland

In this paper, a pipeline architecture supporting both 8 /spl times/ 8 discrete cosine transform (DCT) and its inverse is described. A regular two-dimensional algorithm with perfect shuffle topology for DCT is derived. the resulting signal flow graph is mapped vertically onto sequential processing units. A similar pipeline architecture is derived for the inverse transform. the unified architecture is obtained by mapping both previous pipelines onto common resources. the proposed architecture contains three multipliers for 8 /spl times/ 8 transforms and its throughput can be increased with additional pipelining.

关键词： Discrete cosine transforms Pipeline processing Computer architecture Arithmetic Discrete transforms Topology throughput Video compression Signal processing parallel architectures

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