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检索条件"任意字段=9th International Conference on Algorithms and Architectures for Parallel Processing"

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Neural networks in FPGAs

Neural networks in FPGAs

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international conference on Neural Information processing

作者： A.R. Omondi J.C. Rajapakse School of Informatics and Engineering Flinders University Bedford Park SA Australia School of Computer Engineering Nanyang Technological University Singapore

As FPGAs have increasingly become denser and faster, they are being utilized for many applications, including the implementation of neural networks. Ideally, FPGA implementations, being directly in hardware and having parallelism, will have performance advantages over software on conventional machines. But there is a great deal to be done to make the most of FPGAs and to prove their worth in implementing neural networks, especially in view of past failures in the implementation of neurocomputers. this paper looks at some of the relevant issues.

关键词： Neural networks Intelligent networks Field programmable gate arrays Hardware Software performance parallel processing Arithmetic Microprocessors Software algorithms Informatics

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Digital signatures and public key cryptosystems with multilayer perceptrons

Digital signatures and public key cryptosystems with multila...

引用

international conference on Neural Information processing

作者： L.P. Yee L.C. De Silva Department of Electrical and Computer Engineering National University of Singapore Singapore

Popular secure public key cryptosystems such as RSA and Diffie-Hellman are based on hard problems like factorization and discrete logarithms. these systems often require large prime numbers the size of 300 decimal digits long for the systems to be secure. the generation of large prime numbers is difficult, and larger prime numbers will be required as advances in parallel computing makes factorization of large numbers faster. In this paper, algorithms for digital signatures and public key cryptosystems using multilayer perceptrons (MLPs) are proposed. the security of the algorithm is based on the difficult problem of solving non-linear simultaneous equations. Instead of needing large prime numbers, the algorithm requires multiple real numbers that can be easily generated.

关键词： Digital signatures Public key cryptography Multilayer perceptrons Neurons Public key Nonlinear equations Drives parallel processing Data security Proposals

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On designing digit multipliers

On designing digit multipliers

引用

IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： C. Nibouche M. Nibouche Fac. of Informatics Ulster Univ. Magee UK Faculty of Informatics The University of Ulster at Magee

the folding and unfolding techniques cannot be used to design pipelined digit adders because of the presence of feedback loops. In this paper, approaches for the design of digit multipliers that can be pipelined to the bit level are presented. It includes architectures obtained via unfolding, the high radix approach and the multi-pipe approach. the pipelining of these architectures has been made possible thanks to a new "pipelined digit adder". the presented architectures are scalable, systolic and can offer a great flexibility in finding the best trade-off between hardware cost and throughput rate by changing the level of pipelining and the digit size.

关键词： Pipeline processing Digital signal processing Feedback loop Hardware Clocks Arithmetic Adders Costs Image processing Computer architecture

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the implementation of GA processor with multiple operators, based on subpopulation architecture

The implementation of GA processor with multiple operators, ...

引用

international conference on Neural Information processing

作者： Minsok Cho Suckwoo Chung Duckjin Chung Integrated Circuit Research Laboratory School of Information & Communication Engineering Inha University Incheon South Korea

ISBN: (纸本)9810475241

We propose the hardware-oriented genetic algorithm processor with efficient exploration based on a subpopulation architecture for high-performance convergence and reducing computation time. We applied the steady-state model among continuous generation model, modified tournament selection, special survival condition and the parallelism of coarse-grain to our proposed GAP. In addition, the crossover operator selection method with respect to the convergence state of each subpopulation was newly employed. In order to implement the efficient hardware structure, the pipelined structure was used. the proposed GAP is implemented on the AGENT2000 board with EFP10K200SRC device.

关键词： Steady-state Hardware Convergence Electronic mail Constraint optimization Laboratories Genetic engineering Genetic algorithms Computer architecture parallel processing

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A new approach to the analysis of Petri nets: parallel processes and predictability of scenarios

A new approach to the analysis of Petri nets: parallel proce...

引用

international conference on Neural Information processing

作者： N.F. Shakirova Moscow Institute of Physics and Technology Moscow Russia

We suggest a new approach to the analysis of Petri nets. It consists of extracting pairs of independent (parallel) transitions, constructing the set of auxiliary objects of those pairs, and treating it on the basis of natural and obvious rules. this allows one to extract all possible scenarios in the behavior of Petri nets and to evaluate their probability-like characteristics in the case of several scenarios.

关键词： Petri nets Physics Process control Tree graphs

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parallelizing the data cube 1

引用

8th international conference on Database theory (ICDT 2001)

作者： Dehne, F Eavis, T Hambrusch, S Rau-Chaplin, A Carleton Univ Sch Comp Sci Ottawa ON K1S 5B6 Canada Dalhousie Univ Fac Comp Sci Halifax NS B3H 1W5 Canada Purdue Univ Dept Comp Sci W Lafayette IN 47907 USA

ISBN: (数字)9783540445036

ISBN: (纸本)9783540414568

this paper presents a general methodology for the efficient parallelization of existing data cube construction algorithms. We describe two different partitioning strategies, one for top-down and one for bottom-up cube algorithms. Both partitioning strategies assign subcubes to individual processors in such a way that the loads assigned to the processors are balanced. Our methods reduce inter processor communication overhead by partitioning the load in advance instead of computing each individual group-by in parallel. Our partitioning strategies create a small number of coarse tasks. this allows for sharing of prefixes and sort orders between different group-by computations. Our methods enable code reuse by permitting the use of existing sequential (external memory) data cube algorithms for the subcube computations on each processor. this supports the transfer of optimized sequential data cube code to a parallel setting. the bottom-up partitioning strategy balances the number of single attribute external memory sorts made by each processor. the top-down strategy partitions a weighted tree in which weights reflect algorithm specific cost measures like estimated group-by sizes. Both partitioning approaches can be implemented on any shared disk type parallel machine composed of p processors connected via an interconnection fabric and with access to a shared parallel disk array. We have implemented our parallel top-down data cube construction method in C++ with the MPI message passing library for communication and the LEDA library for the required graph algorithms. We tested our code on an eight processor cluster, using a variety of different data sets with a range of sizes, dimensions, density, and skew. Comparison tests were performed on a SunFire 6800. the tests show that our partitioning strategies generate a close to optimal load balance between processors. the actual run times observed show an optimal speedup of p.

关键词： OLAP data cube parallel processing partitioning load balancing

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Architectural improvements and FPGA implementation of a multimodel neuroprocessor

Architectural improvements and FPGA implementation of a mult...

引用

international conference on Neural Information processing

作者： I.Z. Mihu H.V. Caprita Computer Science Department Lucian Blaga University of Sibiu Sibiu Romania

Since neural networks (NNs) require an enormous amount of learning time, various kinds of dedicated parallel computers have been developed. In the paper a 2-D systolic array (SA) of dedicated processing elements (PEs) also called systolic cells (SCs) is presented as the heart of a multimodel neural-network accelerator. the instruction set of the SA allows the implementation of several neural algorithms, including error back propagation and a self organizing feature map algorithm. Several special architectural facilities are presented in the paper in order to improve the 2-D SA performance. A swapping mechanism of the weight matrix allows the implementation of NNs larger than 2-D SA. A systolically propagated instruction word accompanying each input vector inside the 2-D SA allows the operating mode to be changed progressively, avoiding intermediate inactive cycles inside the 2-D SA. An FPGA implementation of the proposed 2-D SA is presented.

关键词： Field programmable gate arrays Neural networks Neurons Application software Equations Prototypes Computer science Pattern recognition Image processing Computer networks

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Time constrain optimal method to find the minimum architectures for feedforward neural networks 9th

Time constrain optimal method to find the minimum architectu...

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international conference on Neural Information processing

作者： Teck-Sun Tan Guang-Bin Huang School of Electrical and Electronic Engineering Nanyang Technological University Singapore

ISBN: (纸本)9810475241

Huang, et al. (1996, 2002) proposed architecture selection algorithm called SEDNN to find the minimum architectures for feedforward neural networks based on the Golden section search method and the upper bounds on the number of hidden neurons, as stated in Huang (2002) and Huang et al. (1998), to be 2/spl radic/((m + 2)N) or two layered feedforward network (TLFN) and N for single layer feedforward network (SLFN) where N is the number of training samples and m is the number of output neurons. the SEDNN algorithm worked well with the assumption that time allowed for the execution of the algorithm is infinite. this paper proposed an algorithm similar to the SEDNN, but with an added time factor to cater for applications that requires results within a specified period of time.

关键词： Time factors Neural networks Feedforward neural networks Neurons Network topology Electronic mail Search methods Upper bound Cost function

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Exploiting the prefetching effect provided by executing mispredicted load instructions 8th

引用

8th international Euro-Par conference on parallel processing, Euro-Par 2002

作者： Sendag, Resit Lilja, David J. Kunkel, Steven R. Department of Electrical and Computer Engineering Minnesota Supercomputing Institute University of Minnesota 200 Union St. S.E MinneapolisMN55455 United States IBM RochesterMN United States

ISBN: (纸本)3540440496

As the degree of instruction-level parallelism in superscalar architectures increases, the gap between processor and memory performance continues to grow requiring more aggressive techniques to increase the performance of the memory system. We propose a new technique, which is based on the wrong-path execution of loads far beyond instruction fetch-limiting conditional branches, to exploit more instruction-level parallelism by reducing the impact of memory delays. We examine the effects of the execution of loads down the wrong branch path on the performance of an aggressive issue processor. We find that, by continuing to execute the loads issued in the mispredicted path, even after the branch is resolved, we can actually reduce the cache misses observed on the correctly executed path. this wrong-path execution of loads can result in a speedup of up to 5% due to an indirect prefetching effect that brings data or instruction blocks into the cache for instructions subsequently issued on the correctly predicted path. However, it also can increase the amount of memory traffic and can pollute the cache. We propose the Wrong Path Cache (WPC) to eliminate the cache pollution caused by the execution of loads down mispredicted branch paths. For the configurations tested, fetching the results of wrong path loads into a fully associative 8-entry WPC can result in a 12% to 39% reduction in L1 data cache misses and in a speedup of up to 37%, with an average speedup of 9%, over the baseline processor. © Springer-Verlag Berlin Heidelberg 2002.

关键词： parallel processing systems

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Validated cost models for parallel OQL query processing 8th

引用

8th international conference on Object-Oriented Information Systems, OOIS 2002

作者： Mendes Sampaio, Sandra de F. Paton, Norman W. Smith, Jim Watson, Paul Department of Computer Science University of Manchester ManchesterM13 9PL United Kingdom Department of Computing Science University of Newcastle upon Tyne NewcastleNE1 7RU United Kingdom

ISBN: (纸本)3540440879

Query cost models are widely used, both for performance analysis and for comparing execution plans during query *** essence, a cost model predicts where time is being spent during query evaluation. Although many cost models have been proposed, for serial,parallel and distributed database systems, surprisingly few of these have been validated against real systems. this paper presents cost models forthe parallel evaluation of ODMG OQL queries, which have been compared with experimental results obtained using the Polar object database system. the paper describes the validation of the cost model for a collection of queries, using three join algorithms over the OO7 benchmark database. the results show that the cost model generally both ranks alternative plans appropriately, and gives a useful indication of the response times that can be expected from a plan. the paper also illustrates the application of the cost model by highlighting the contributions of different features and operations to query response times. © Springer-Verlag Berlin Heidelberg 2002

关键词： Distributed database systems

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