this paper presents the design of a dedicated parallel architecture for connected component analysis. Categorized in one-dimensional array processors, for an image of n/spl times/n pixels, the proposed architecture ha...
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Withthe increasing complexity of VLSI circuits, simulation of digital circuits is becoming a more complex and time-consuming task. General purpose parallelprocessing machines are increasingly being used to speed up ...
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Withthe increasing complexity of VLSI circuits, simulation of digital circuits is becoming a more complex and time-consuming task. General purpose parallelprocessing machines are increasingly being used to speed up a variety of VLSI CAD applications. All previous works on mapping sequential logic simulation algorithms onto general purpose parallel machines were centered around using event-driven algorithm, and do not satisfactorily address the suitability of a particular sequential algorithm for parallel implementation. In this paper, we present analysis of two distributed simulation algorithms: the centralized-time event-driven algorithm and the time-first evaluation algorithm, mapped onto a network of workstations. We present results over a wide range of ISCAS85 and ISCAS89 benchmark circuits, to show that the time-first evaluation algorithm is likely to be a viable alternative to the event-driven algorithm in the domain of parallel logic simulation.
the proceedings contain 63 papers. the special focus in this conference is on Knowledge Representation, Learning and Discovery Systems. the topics include: Learning composite concepts in description logics;comparison ...
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(纸本)9783540612865
the proceedings contain 63 papers. the special focus in this conference is on Knowledge Representation, Learning and Discovery Systems. the topics include: Learning composite concepts in description logics;comparison of conceptual graphs for modeling knowledge of multiple experts;semantical considerations for knowledge base updates;partial evaluation in constraint logic programming;the AQI 7-DCI system for data-driven constructive induction and its application to the analysis of world economics;induction of classification rules from imperfect data;induction of expert system rules from databases based on rough set theory and resampling methods;mining patterns at each scale in massive data;on evolving intelligence;intelligent mutation rate control in canonical genetic algorithms;a fine-grained parallel evolutionary program for concept induction;evolutionary exploration of search spaces;evolutionary computation;signed formula logic programming;automating proofs of integrity constraints in situation calculus;towards programming in default logic;on the formal specification of temporal deontic constraints;validity queries and completeness queries;explanation for cooperative information systems;toward intelligent representation of database content;reducing information systems with uncertain attributes;object and dependency oriented programming in FLO;knowledge simplification;a model-based approach to consistency-checking;resource-based vs task-based approaches for scheduling problems;a fuzzy behaviorist approach to sensor-based robot control;knowledge-based fuzzy neural networks;coevolutionary game theoretic multi-agent systems;searching for features defined by hyperplanes;inductive database design and enhancing query processing of information systems.
this paper presents VLSI/WSI designs for a recently introduced parallel architecture known as the folded cube-connected cycles (FCCC). We first discuss two layouts for the FCCC, in which there is no component redundan...
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this paper presents VLSI/WSI designs for a recently introduced parallel architecture known as the folded cube-connected cycles (FCCC). We first discuss two layouts for the FCCC, in which there is no component redundancy. then we incorporate redundancy and present locally and globally reconfigurable FCCCs. We also discuss the design of universal building blocks for the construction of fault-tolerant FCCCs of various dimensions.
Tree matching is an important problem used for 3D object recognition in image understanding and vision systems. It is also used in the design of on-line interpreter systems as well as code optimization in compilers. T...
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Tree matching is an important problem used for 3D object recognition in image understanding and vision systems. It is also used in the design of on-line interpreter systems as well as code optimization in compilers. the objective of tree matching is to find the set of nodes at which a pattern tree matches a subject tree. Recently, two linear systolic array algorithms have been proposed by the authors. In this paper, we propose an improved approach wherein the the systolic algorithm is based on a linear array of fixed size independent of the problem size and larger strings are partitioned and processed based on the array size. Also, the architecture is simplified by moving the logic for processing variables in each PE to a single PE attached at the end. the systolic algorithm and architecture have been verified through simulation using the Cadence design tools.
the paper presents low power realization of FIR filters using multirate architectures. the multirate architectures enable computationally efficient implementations of FIR filters. the computational complexity of these...
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the paper presents low power realization of FIR filters using multirate architectures. the multirate architectures enable computationally efficient implementations of FIR filters. the computational complexity of these architectures is analysed and power analysis is presented to show how the computational efficiency can be exploited to reduce power dissipation. the results show upto 73% power reduction for dedicated ASIC implementation with no datapath area overhead. the paper also presents the implementation of the multirate architecture on the TMS320C2x/C5x programmable DSPs and shows that it can result in upto 43% power reduction.
Finite field has received a lot of attention due to its widespread applications in cryptography, coding theory, etc. Design of efficient finite field arithmetic architectures is very important and of great practical c...
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Finite field has received a lot of attention due to its widespread applications in cryptography, coding theory, etc. Design of efficient finite field arithmetic architectures is very important and of great practical concern. In this paper, a new bit-serial/parallel finite field multiplier is presented with standard basis representation. this design is regular and well suited for VLSI implementation. As compared to existing serial/parallel finite field multipliers, it has smaller critical path, lower latency and can be easily pipelined. When it is used as a building block for large systems, it can achieve more savings in hardware in the broadcast structures by utilizing sub-structure sharing technique. this paper also presents two generalized algorithms for finite field serial/parallel multiplication. they can be used to derive efficient bit-parallel, digit-serial or bit-serial multiplication architectures. the optimal primitive polynomials over GF(2/sup m/) (for 2/spl les/m/spl les/9) are provided which will generate structures with minimum hardware complexity and relatively more flexibilities for feasible digit-sizes with respect to the proposed algorithms. Finally a multiplier over GF(2/sup 8/) is given as an example showing how to derive finite field multipliers using the proposed algorithms. this multiplier has less number of transistors, smaller critical path and consumes less power compared to the existing semi-systolic architecture.
We present a graph based approach to the time (performance) constrained synthesis of multi-chip module (MCM) architectures. System-level partitioning is performed using the Stochastic Evolution heuristic, which is an ...
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We present a graph based approach to the time (performance) constrained synthesis of multi-chip module (MCM) architectures. System-level partitioning is performed using the Stochastic Evolution heuristic, which is an effective heuristic for solving several combinatorial optimization problems. the partitioning cost function models the scheduling/allocation constraints (including interchip buses) in the form of incompatible sets. Supernodes are created using the scheduling/allocation constraints which in turn reduces the search space for the partitioner. Scheduling and resource allocation is performed for the case of time (performance) constrained synthesis and includes modeling of inter-chip buses, multi-cycle operations, pipelined functional units and functional pipelining. Efficient synthesis results are obtained for the high-level synthesis benchmarks in far less CPU time compared to the integer linear programming based model.
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