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检索条件"任意字段=9th International Conference on Algorithms and Architectures for Parallel Processing"

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A highly-parallel architecture for concurrent rule match of AI production systems

A highly-parallel architecture for concurrent rule match of ...

引用

IEEE Region 10 international conference TENCON

作者： Chie Dou Department of Electrical Engineering National Yunlin Institute of Technology Yunlin Taiwan

ISBN: (纸本)0780318625

In this paper, a highly-parallel architecture for concurrent rule match is proposed to speed up the execution time of match process of AI production systems. the architecture fully exploits the advantages of content addressable memory (CAM) not only to buffer the database of current assertions, called the working memory (WM), but also to support the functions of parallelly evaluating interconditions among patterns of productions. the architecture first compiles the left-hand side (LHS) of each production into a symbolic form and then assigns a CAM cell array, called CAM block, to each production for buffering elements as well as evaluating interconditions. the set of productions that are affected during a match cycle can be evaluated concurrently and independently within their own CAM blocks. Due to the uniformity of constructing arrays of processing elements by CAM block, the novel architecture is suitable for VLSI implementation. the analysis of the expected performance indicates that the novel architecture might speed up conventional forward-chaining production systems by perhaps a factor of 100 or higher.< >

关键词： Artificial intelligence Production systems Computer aided manufacturing CADCAM Computer architecture Databases parallel processing Very large scale integration Performance analysis Knowledge based systems

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parallel computing efficiency: climbing the learning curve

Parallel computing efficiency: climbing the learning curve

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IEEE Region 10 international conference TENCON

作者： E.T. Kumm R.M. Lea Aspex Microsystems Limited Brunel University Uxbridge Middlesex UK

parallel computing shows considerable potential to deliver cost-effective solutions to applications with high requirements in performance. However, current experience shows that performance often falls well below user expectations and below what would be considered cost-effective. therefore, MPC hardware and software designers need to focus on the factors which affect parallel computing efficiency, if they are to narrow the gap between potential and delivered performance. Many analyses of parallel computing efficiency which have been reported are mainly too restrictive to provide helpful results. thus, a different approach is required which would help parallel architecture and algorithm designers to climb the learning curve associated with parallel computing efficiency. In this paper, a performance analysis is introduced which makes a distinction between natural parallelism (which is inherent to an application) and applied parallelism (which can be observed when an application is implemented on an MPC). By highlighting parallel computing bottlenecks the analysis supports MPC hardware and software designers to identify causes for inefficiency. Furthermore helpful efficiency measures can be defined. the paper demonstrates the usefulness of the analysis and concludes that it could form the basis of a methodology which formalises the improvement of parallel computing efficiency.< >

关键词： parallel processing Application software Concurrent computing Software design Software performance Algorithm design and analysis Performance analysis Hardware Computational modeling Context modeling

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Digital reconstruction of Fourier optical signal using efficient 24-bit floating point multiply-add-subtract module

Digital reconstruction of Fourier optical signal using effic...

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IEEE Region 10 international conference TENCON

作者： A. Wahab Tan Beng Heok S.S. Erdogan School of Applied Science Division of Computer Technology Nanyang Technological University Singapore Singapore

this paper describes a practical Fourier optical signal processor (FOSP) as a pre-processor for digital signal processing (DSP). the input illumination is a coherent light source from a HeNe laser and computation of the Fourier Transform (FT) is carried out via an FT lens. An image is placed in the front focal plane of the FT lens and at the back focal plane of the lens, the Fourier transform image results. Using the method reported by Xu (1988) for the measurement of the phase information the real and imaginary information is retrieved and fed electronically into a Fast Fourier Transform (FFT) module, using 24-bit floating point units capable of performing efficient multiplication, addition and subtraction to reconstruct the original image. Many of such floating-point units are used in parallel in a pipelined architecture to perform FFT or other complex function for digital signal processing (DSP) computations.< >

关键词： Digital signal processing Lenses Image reconstruction Optical signal processing Fourier transforms Signal processing Lighting Light sources Phase measurement Information retrieval

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parallel implementation of an adaptive and iterative noise filter for efficient signal restoration

Parallel implementation of an adaptive and iterative noise f...

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IEEE Region 10 international conference TENCON

作者： Hong Tang Bingbing Zhou I. Macleod R. Brent Wei Sun Computer Science Laboratory Research School of Information Sciences and Engineering Australian National University Canberra ACT Australia

In signal restoration, especially image restoration, there are tremendous demands for large volume and high speed computations. the paper describes application of a novel noise filter, the adaptive differential iterative RMS filter (ADIRMS), to restoration of noisy signals without any a priori information regarding the signal. An efficient parallel implementation of the filter on distributed memory MIMD machines is outlined. Since the local memory in each processing element (PE) of the system is accessible to other PEs only via explicit message passing, the manner of data distribution and communication is a very important factor for efficient solution of a given problem; this issue is considered in some detail. the ADIRMS algorithm has been implemented on the Fujitsu AP1000 with high efficiency. We conclude that this algorithm provides a good basis for parallel implementation on distributed memory machines.< >

关键词： Adaptive filters Signal restoration Pixel Information filtering Information filters Concurrent computing Degradation Image restoration Distributed computing Additive noise

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Simulation and performance evaluation of parallel architecture based on i860 nodes: SapePar-i860

Simulation and performance evaluation of parallel architectu...

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IEEE Region 10 international conference TENCON

作者： A. Pandlan K. Parthasarathy M.K. Sridhar K.C. Gowda Dept. of Electr. Eng. Indian Inst. of Sci. Bangalore India Department of Electrical Engineering Indian Institute of Science Bangalore India National University of Singapore Singapore Department of Computer Science S J College of Engineering Mysore India

SapePar-i860 is an execution driven "Simulator and Performance Evaluator for i860 based parallel Architecture". the simulator has various inputs like the primary cache size, primary cache type, secondary cache size, secondary cache type, secondary cache replacement policy, number of processors, interconnection between the processors, communication path from each processor to other processors, type of communication and bandwidth of communication channels. the simulator gets configured automatically according to the inputs and generates log files. the performance analyzer generates statistics of the run based on these log files. the statistics includes cache hit ratio of primary cache, cache hit ratio of secondary cache, Complete Communication Ratio (CCR/sub i/) of each processor, the Compute Communication Ratio (CCR/sub 6/) of overall system, efficiency of each processor and efficiency of overall system. this also computes the speedup, execution time in terms of clock ticks.< >

关键词： parallel architectures Computer architecture Performance analysis Pipelines Program processors Computational modeling Computer science Performance evaluation Communication channels Statistics

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Scheduling task graphs onto heterogeneous multiprocessors

Scheduling task graphs onto heterogeneous multiprocessors

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IEEE Region 10 international conference TENCON

作者： Dingchao Li N. Ishii Education Center for Information Processing Nagoya Institute of Technology Nagoya Japan Department of Intelligence and Computer Science Nagoya Institute of Technology Nagoya Japan

In a heterogeneous system, the efficient exploitation of parallelism requires scheduling strategies that account for heterogeneity among processors to achieve an effective mapping of computations to processors. the paper presents a scheduling heuristic specialized for heterogeneous multiprocessor systems which make use of several different types of processors. the new algorithm is based on the greedy strategy: no processor remains idle if there is some task available that it could process. A graph called the classified typed task graph is used to describe the current status of tasks of different types at each scheduling step. With the graph, the algorithm dynamically evaluates the priorities of tasks only when there are multiply executable candidates, and then schedules an appropriate one onto the currently available processors of the corresponding type. A preliminary evaluation shows that this algorithm has promising performance.< >

关键词： Processor scheduling Optimal scheduling Scheduling algorithm Multiprocessing systems Dynamic scheduling Computer science education Information processing Computer science Educational technology parallel processing

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An execution order control method of distributed processes for sharing global variables

An execution order control method of distributed processes f...

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IEEE Region 10 international conference TENCON

作者： K. Asakura T. Watanabe N. Sugie Department of Information Engineering Faculty of Engineering University of Nagoya Nagoya Japan

the parallelizing compiler divides a given program into several processes which can be executed simultaneously in a distributed computer environment. However, a program has global variables generally. therefore, the processes have to share global variables since they are common in the program. In order to manage global variables correctly, the processes need to possess the broadcasting facility for data sharing and the synchronization facility for execution order control among the processes. We propose execution order control methods among the processes for sharing global variables in the distributed computer environment.< >

关键词： Distributed control Distributed computing Concurrent computing Computer networks Process control parallel processing Hardware Communication system control Workstations Local area networks

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parallel implementation of simulated annealing using transaction processing: a preliminary study

Parallel implementation of simulated annealing using transac...

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IEEE Region 10 international conference TENCON

作者： D.C.W. Pao Department of Electronic Engineering City Polytechnic of Hong Kong Hong Kong China

Simulated annealing is an effective method for solving large combinatorial optimization problems. It has been successfully applied to the cell placement and routing problem of VLSI circuit design and to other classical optimization problems such as the traveling salesman problem and the graph partitioning problem. One major drawback of simulated annealing is that it requires a substantial amount of computation time. In this paper, we present a new parallel implementation of simulated annealing which is based on the concurrency control theory of database systems. the parallelized computation is serializable. Hence, the result obtained is equivalent to a serial execution of the original sequential annealing algorithm. In our implementation, we assume a shared-memory MIMD multiprocessing environment with 16 to 32 processors. Preliminary analysis shows that our method is able to achieve an efficiency (ratio of speedup to the number of processors) of from about 40 to over 90%, depending on the acceptance rate.< >

关键词： Simulated annealing Circuit simulation Computational modeling Optimization methods Routing Very large scale integration Circuit synthesis Design optimization Traveling salesman problems Concurrency control

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Programmed graph reduction based on function granularity and its parallel implementation

Programmed graph reduction based on function granularity and...

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IEEE Region 10 international conference TENCON

作者： Dae Wook Bang Yoo Kun Cho Department of Computer Science Keimyung University Taegu South Korea Department of Computer Engineering Seoul National University Seoul South Korea

ISBN: (纸本)0780318625

this paper examines closely the implementation problems-code execution, global memory access, and graph distribution of the programmed graph reduction machine based on function granularity, and proposes their solutions. Our function-grained graph reduction machine enables tasks to reduce the graph nodes that represent function applications. Each processing element executes multiple tasks concurrently, and manages itself with its own image of the operating system. In the implementation of this machine, we represented a machine code as a macro instruction that calls a predefined program, and devised DSM system that makes PEs access a virtual global memory but delays sending the update to the remote page until execution of a machine code is terminated successfully. We used the dipstick scheduling strategy, which combines both the partition and the distribution strategies to allocate graph nodes to PEs. We also showed the evaluation results that are experimented on the prototype machine.< >

关键词： Computer science Operating systems Delay Scheduling Distribution strategy Computational modeling Prototypes

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Rolling mapping/mesh: a mapping method/interconnection structure for a mesh with various densities

Rolling mapping/mesh: a mapping method/interconnection struc...

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IEEE Region 10 international conference TENCON

作者： A. Murata H. Amano Department of Living Science Kyoto Prefectural University Kyoto Japan Department of Computer Science Keio University Yokohama Japan

In order to solve the partial differential equations (PDEs), the target physical region is divided into a nearest neighbor mesh (NNM). Although a dense mesh improves the accuracy of the solution, the computation time is stretched with a large amount of calculation. thus, a mesh with partially varied densities improves the accuracy locally without explosion of the computation cost. For calculations of PDEs, parallel machines in which processing units (PUs) are connected with an NNM connection structure have been utilized because the required communication is usually matched with the connection structure. However, if a mesh with various densities is utilized, the PU-assigning algorithm (mapping) becomes difficult. Conventional mapping methods increase communication between remote PUs and require the cyclic links for the PU array. Here, we propose a mapping method called the rolling mapping for assigning tasks of the PDE into multiprocessor with the NNM structure. Using this method, the mesh with various densities are mapped into PU array without cyclic links nor increasing the data exchange between remote PUs. With the scheduling method, the overhead caused by remaining remote communication can be hidden as possible. An extended NNM structure called the rolling mesh is also proposed. With this structure, every message can be communicated directly between PUs.< >

关键词： Computational efficiency parallel machines Nearest neighbor searches Partial differential equations Physics computing Explosions Computer science Concurrent computing Degradation

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