the performance of the ASP computer on vision tasks has been evaluated by applying the Abingdon Cross benchmark using a number of different algorithms. In this paper, these algorithms are compared and contrasted on th...
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the performance of the ASP computer on vision tasks has been evaluated by applying the Abingdon Cross benchmark using a number of different algorithms. In this paper, these algorithms are compared and contrasted on the basis of their performance.< >
Studies the parallel recognition of 2D-images generated by parallel context-free image grammars. the authors show that the recognition of an n*n image can be done in O(log/sup 2/(n)) time with n/sup 6/ processors. For...
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Studies the parallel recognition of 2D-images generated by parallel context-free image grammars. the authors show that the recognition of an n*n image can be done in O(log/sup 2/(n)) time with n/sup 6/ processors. For unambiguous context-free and linear image grammars, they prove that only O(n/sup 3/) is needed. For deterministic parallel image grammars, the recognition can be done in O(log/sup 2/(n)) time by using n/sup 2/ processors.< >
作者：
Yeh, Hong-JinLIP-IMAG
Ecole Normale Supérieur de Lyon 46 Allée d’Italie Lyon Cédex 0769364 France
In this paper, we present a task scheduling algorithm which accounts for digit-level pipelines of on-line arithmetic units when a limited number of heterogeneous on-line arithmetic units can be connected totally with ...
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Describes a parallel computing system and a software algorithm for realtime interaction between a human user and a synthesized moving humanlike image or agent. the realistic human-like agent appearing on a display can...
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Describes a parallel computing system and a software algorithm for realtime interaction between a human user and a synthesized moving humanlike image or agent. the realistic human-like agent appearing on a display can recognize the palm position and finger motion (finger sign) of the human user, then tracks and gazes at the hand position and changes his/her facial expression in response to the recognized finger sign in realtime. this kind of interactive agent is expected to play an important role in advanced human interfaces. To realize realtime image recognition and image synthesis, a parallel image processing and synthesis system named 'TN-VIT' has been developed.< >
Quadtree region representation, image properties computation of binary image and moment invariants are implemented on a pyramid machine. Based on those algorithms a parallel pattern recognition technique is proposed. ...
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Quadtree region representation, image properties computation of binary image and moment invariants are implemented on a pyramid machine. Based on those algorithms a parallel pattern recognition technique is proposed. Exploiting the parallel quadtree representation on pyramid machine, moment invariants seems to be a good descriptor in a hierarchical coarse-fine matching strategy. For a particular image, the moment invariants always changes slightly at higher levels in the representation. A matching criteria of distance measure can be used to find dissimilarity in images.< >
A method called concentration-contour method is presented. It transforms a compound pattern into an integral one where contour analysis can be used. the concentration-contour method consists of four phases: (1) concen...
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A method called concentration-contour method is presented. It transforms a compound pattern into an integral one where contour analysis can be used. the concentration-contour method consists of four phases: (1) concentration of pattern, (2) extraction of contour, (3) transformation of numerical features, and (4) classification. the diagonal-diagonal regional projection transformation (DDRPT), which converts a compound pattern into an integral object, has been used. A VLSI architecture to implement the concentration-contour approach has been designed. the time complexity of the method is only O(N) compared with O(N/sup 2/) when a uniprocessor is used.< >
Several methods for parallel affine image warping on a linear processor array are considered. the methods were implemented on the Carnegie Mellon Warp machine and the Carnegie Mellon-Intel Corporation iWarp computer (...
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Several methods for parallel affine image warping on a linear processor array are considered. the methods were implemented on the Carnegie Mellon Warp machine and the Carnegie Mellon-Intel Corporation iWarp computer (treated as a linear array), and performance figures are provided. Both systolic methods, which feed one of the images in a stream, and non-systolic methods, which partition both images, are treated. A scanline method that combines some of the features of both, but which requires a fast transposed method is also described. the authors articulate three characteristics that affect the design of parallel image warping algorithms: affine warping is easily invertible, the mapping is known at the start of execution, and nearby input pixels map to nearby output pixels. the authors conclude that non-systolic methods give slightly better execution time and are easier to programs than systolic methods but require much larger processor memories.< >
A VLSI parallel and distributed computation algorithm has been proposed and mapped onto a VLSI architecture for a 1-D discrete cosine transform (DCT) involving the symmetry property. In this 1-D DCT processor architec...
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ISBN:
(纸本)0818620307
A VLSI parallel and distributed computation algorithm has been proposed and mapped onto a VLSI architecture for a 1-D discrete cosine transform (DCT) involving the symmetry property. In this 1-D DCT processor architecture, there are (log2N + 1) DCT processor units (PUs) required for computation of a frame of N-point data with a time complexity of O(N). Further, a 2-D DCT processor architecture has been proposed withthe input buffer of an (M × 1) 1-D N-point DCT processor array required for computation of the M frames of N-point input data and the output buffer of a (1 × N) 1-D M-point DCT processor array required for permutation of the N frames of M-point output data, so that the total number of DCT PUs required is (M(log2N + 1) + N(log2M + 1)) with a time complexity of O(M + N). Both of the 1-D and 2-D DCT processor architectures can be controlled by firmware;hence they are more flexible, efficient, and fault tolerant and, therefore, very suitable for VLSI implementation.
A message-passing multicomputer is presented, and its application to image processing and reconstruction is outlined. the multicomputer may be seen as a one-dimensional array of computing nodes with bidirectional shuf...
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A message-passing multicomputer is presented, and its application to image processing and reconstruction is outlined. the multicomputer may be seen as a one-dimensional array of computing nodes with bidirectional shuffle and shift connections. the resulting shuffle-shift machine is well suited for tasks like image processing and image reconstruction. A sample shuffle-shift machine has been built using transputers. the hardware and software aspects of this implementation are described, and benchmark results obtained with a number of image-oriented algorithms are included. the shuffle-shift machine is compared with related parallel computer architectures, and a two-dimensional generalization is indicated.
A system for dynamic intelligent scheduling and control (DISC) of reconfigurable parallel processors is presented. the purpose of the system is to provide a rapid prototyping capability for computer vision/image proce...
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A system for dynamic intelligent scheduling and control (DISC) of reconfigurable parallel processors is presented. the purpose of the system is to provide a rapid prototyping capability for computer vision/image processing tasks. the scheduler particularly addresses the problems of algorithms with execution times that depend on the image data and processing scenarios that vary dynamically based on the input image. Since conventional scheduling methods cannot propose schedules for most masks of this type, a dynamic controller is used to schedule the task and reconfigure the machine on the fly. this dynamic scheduling system attempts to balance the overall processing scenario withthe needs of the individual routines that make up the task. the implementation of this system is discussed, with emphasis on the scheduling heuristics and the use of the system for prototyping computer vision/image processing tasks. Testing was done on a number of tasks that exercised different aspects of the scheduling strategy. the schedules determined by DISC have an average tiling percentage of 77% and an average scheduling overhead of only 0.1% of the total task execution time.
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