the binary predicate execution model (BPEM) is a computational model that combines logic programming, semantic nets, and message-driven computation into a paradigm for the construction of highly parallel knowledge-bas...
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the binary predicate execution model (BPEM) is a computational model that combines logic programming, semantic nets, and message-driven computation into a paradigm for the construction of highly parallel knowledge-base systems. Simulation results are presented that demonstrate the ability of BPM to exploit effectively the resources of a loosely coupled computer network consisting of large numbers of independent processing elements. these simulations suggest performance on the order of 10/sup 5/ logical inferences per second for 256 processing elements in an n-cube configuration. A very important feature of the BPEM is that it scales-up linearly under simple OR-parallelism and AND-parallelism. Hence, the BPEM can scale-up to exploit parallelism efficiently in very large semantic networks and knowledge bases.< >
Four distributed query processing strategies under consideration for incorporation into the Cronus object-oriented distributed computing environment are described. Under Cronus, object storage can be embedded inside a...
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Four distributed query processing strategies under consideration for incorporation into the Cronus object-oriented distributed computing environment are described. Under Cronus, object storage can be embedded inside applications, and facilities are provided to distribute and replicate automatically the data maintained by the application. the performance of the query processing strategies is analyzed within this environment. the resulting evaluation points out the factors to consider in developing query processing strategies for replicated, object-oriented data, and the impact of those factors on the cost and optimality of the strategies. the evaluation led to the adoption of an optimistic, decentralized strategy which increases parallelism and decreases the size of messages at the expense of an increase in the number of messages transferred.< >
An augmented binary (AB) tree architecture is proposed with a view to providing fault tolerance. this architecture is an augmentation of an n-level full binary tree with n redundant nodes and 2/sup n/+3n-6 redundant l...
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An augmented binary (AB) tree architecture is proposed with a view to providing fault tolerance. this architecture is an augmentation of an n-level full binary tree with n redundant nodes and 2/sup n/+3n-6 redundant links. the AB tree can be configured into a full binary tree even when one node is faulty at each level. While functionally equivalent to the RAE-tree, the proposed AB tree has a regular topology, reduced number of maximum input-output channels per processor, and fewer wire crossovers when implemented using very large-scale integration layout. A reconfiguration algorithm, which constructs an n-level full binary tree from an n-level faulty AB tree, is given. A distributed fault diagnosis algorithm is given which runs concurrently on each nonfaulty processor, enabling each nonfaulty processor to identify all faulty processors.< >
A language paradigm called shared dataspace is defined that causes computations to be performed using an anonymous, content-addressable communication medium acted upon by atomic transactions. To probe the essence of t...
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A language paradigm called shared dataspace is defined that causes computations to be performed using an anonymous, content-addressable communication medium acted upon by atomic transactions. To probe the essence of this paradigm, a relatively simple shared dataspace language called Swarm is defined. An overview is presented of the Swarm language. A formal operational model for the language is given and some of the programming implications and distinctive features of the model and language are discussed. Swarm programming strategies are examined using a series of related example programs.< >
A system is described that combines the major strengths of local area networks and multicomputers, namely resource sharing over geographically significant distances and small communication latencies. the result is a n...
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A system is described that combines the major strengths of local area networks and multicomputers, namely resource sharing over geographically significant distances and small communication latencies. the result is a new architecture called a local area multicomputer (LAM). the system that is described attempts to solve the seemingly incompatible needs of the two application domains by utilizing a high-capacity, low-latency interconnection network called the HPC supported by the VORX multiprocessor computing environment. For systems with hundreds of nodes, the network capacity is in the Gb/s range, and the latency for small messages is about 10 mu s. the HPC can connect resources located several kilometers apart. the VORX environment provides the necessary program development tools and resource management functions needed to experiment with distributed applications. Two applications are outlined to show the diverse uses for a LAM system and the status of an 80-node system that includes 70 adjunct processors and ten SUN 3 workstations/fileservers.< >
the complexity of efficiently programming massively parallel machines is illustrated by presenting a number of new algorithms. these algorithms deal with computational geometry, data histogramming, list manipulation, ...
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ISBN:
(纸本)0818608781
the complexity of efficiently programming massively parallel machines is illustrated by presenting a number of new algorithms. these algorithms deal with computational geometry, data histogramming, list manipulation, and other problems or operations that arise in computer vision tasks. All of the algorithms presented use a divide-and-conquer strategy, and they all use routines that solve a problem of size M using a machine of size N, where M < N. In some of the algorithms, the extra processors are used to perform more than M calculations in parallel. In other algorithms, the extra processors are used to improve the speed of interprocessor communication.
the author reviews a number of parallel-processing projects which tried to conveniently use processing power, memory and input/output of image data for image analysis. the systems covered include ILLIAC, CLIP, MPP, th...
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ISBN:
(纸本)0818608781
the author reviews a number of parallel-processing projects which tried to conveniently use processing power, memory and input/output of image data for image analysis. the systems covered include ILLIAC, CLIP, MPP, the cytocomputer, SNAP, and PAPIA and II. Issues in parallelism reviewed include types of parallelism, types of operation, complexity of processing elements, and the different paradigms of human vision and their application and implementation.
Preprocessing, which plays an important role in pattern recognition, is investigated from the point of view of real-time processing, and a set of one-pass processingalgorithms are described. All of the algorithms, wh...
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ISBN:
(纸本)0818608781
Preprocessing, which plays an important role in pattern recognition, is investigated from the point of view of real-time processing, and a set of one-pass processingalgorithms are described. All of the algorithms, which are based on easy hardware implementation, only require one single cycle of parallel operations per image frame, and the operations are confined in a window of size 3 × 3. Computer simulation shows that the algorithms are efficient and easily realized in hardware.
the magnitude-distance and maximum-value-distance filters are analyzed, and fast realizations are proposed to implement a DRF cascade for edge detection. It is shown that the maximum-value-distance filter is well adap...
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ISBN:
(纸本)0818608781
the magnitude-distance and maximum-value-distance filters are analyzed, and fast realizations are proposed to implement a DRF cascade for edge detection. It is shown that the maximum-value-distance filter is well adapted to parallelprocessing and works two times as fast as the magnitude-distance filter. It is shown also that the adaptive gradient is an optimal estimate for edge-pixel verification after zero-crossing detection. the efficiency of the proposed algorithms is confirmed by experimental results.
OPSILA, is a description given of a general-purpose parallel architecture with two different forms of parallelism: the well-known SIMD (single-instruction, multiple data shown), a synchronous form of parallelism;and S...
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ISBN:
(纸本)0818608781
OPSILA, is a description given of a general-purpose parallel architecture with two different forms of parallelism: the well-known SIMD (single-instruction, multiple data shown), a synchronous form of parallelism;and SPMD (single program, multiple data stream), which is an asynchronous mode. It is shown that OPSILA is efficient for a wide variety of image algorithms including low and high level processing. the efficiency of OPSILA is demonstrated for the low-level algorithms, through the implementation of a set of typical operations: local (convolution), global (histogram), and geometric corrections.
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