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检索条件"任意字段=9th International Conference on Algorithms and Architectures for Parallel Processing"

共 2826 条记录，以下是281-290 订阅

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C3O: Collaborative Cluster Configuration Optimization for Distributed Data processing in Public Clouds 9

C3O: Collaborative Cluster Configuration Optimization for Di...

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9th IEEE international conference on Cloud Engineering (IC2E)

作者： Will, Jonathan thamsen, Lauritz Scheinert, Dominik Bader, Jonathan Kao, Odej Tech Univ Berlin Berlin Germany

ISBN: (纸本)9781665449700

Distributed dataflow systems enable data-parallel processing of large datasets on clusters. Public cloud providers offer a large variety and quantity of resources that can be used for such clusters. Yet, selecting appropriate cloud resources for dataflow jobs - that neither lead to bottlenecks nor to low resource utilization - is often challenging, even for expert users such as data engineers. We present C3O, a collaborative system for optimizing data processing cluster configurations in public clouds based on shared historical runtime data. the shared data is utilized for predicting the runtimes of data processing jobs on different possible cluster configurations, using specialized regression models. these models take the diverse execution contexts of different users into account and exhibit mean absolute errors below 3% in our experimental evaluation with 930 unique Spark jobs.

关键词： Scalable Data Analytics Distributed Dataflows Runtime Prediction Resource Allocation Cluster Management

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Research on cooperative scheduling of production and transportation for unrelated parallel processors 9

Research on cooperative scheduling of production and transpo...

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9th international Symposium on Project Management, ISPM 2021

作者： Shangguan, Yanfeng School of Management Hefei University of Technology Hefei230009 China

ISBN: (纸本)9781921712777

In this paper, we solve the problem of production and transportation coordination scheduling for unrelated parallel processors. the supply chain consists of a single customer and multiple manufacturers located in different geographical locations. Under the condition of limited transportation capacity, we establish an integer programming model for the problem. According to the specific characteristics of the scheduling problem, the work pieces were cod in real number, randomly assigned according to the processing capacity of the batch machine, and then divided into batches through the method BFLPT. And we propose a hybrid algorithm combining the merits of discrete particle swarm optimization (DPSO) and genetic algorithm (GA) for solving this problem. Finally, we compare the DPSO-GA with GA and DPSO in simulation experiments, and verify the superiority of the algorithm. © ISPM *** right reserved.

关键词： Supply chains

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FPGA-Based Lightweight CNN Acceleration System for Real-Time Recognition

FPGA-Based Lightweight CNN Acceleration System for Real-Time...

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international conference on Integrated Circuits and Microsystems (ICICM)

作者： Junlei Ju Cheng Liu School of Microelectronics Shanghai University Shanghai China

ISBN: (数字)9798331509453

ISBN: (纸本)9798331520243

In recent years, convolutional neural networks (CNNs) have become the core of many artificial intelligence applications, especially in fields such as image recognition and speech recognition. Deploying convolutional neural networks in hardware, as opposed to software, can increase speed and reduce power consumption. In this article, we propose an FPGA-based convolutional neural network acceleration system. this system optimizes LeNet-5 into a lightweight convolutional neural network model by replacing traditional convolution with depthwise separable convolutions and reducing the number of fully connected layers. After designing a parallel processing scheme for the computation process of the model, a CNN acceleration IP core is implemented using Verilog and applied to real-time handwritten digit recognition. this system can recognize one frame of image in 326.24µs, which is approximately 1s faster than CPU recognition. the total power consumption of the entire system is 1.947W, meeting the requirements of high real-time performance and low power consumption.

关键词： Handwriting recognition Power demand Image recognition Convolution Computational modeling Speech recognition Real-time systems Central processing Unit Convolutional neural networks Testing

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Ultra Low Power High Speed DFT Implementation For ASIC SoC

Ultra Low Power High Speed DFT Implementation For ASIC SoC

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international conference for Convergence of Technology (I2CT)

作者： K. Madhava Rao Pattem Sampath Kumar T. Vasudeva Reddy D Nilima K Saikumar Abbas Mahdi Khlaif Dept of ECE B V Raju Institute of Technology Narsapur Medak Telangana Department of ECE Malla Reddy College of Engineering Maisammaguda Dhulapally Secunderabad Department of Computer Science and Information Technology MLR Institute of Technology Hyderabad Telangana India Computer Science School of Engineering Malla Reddy University Maisammaguda Dulapally Hyderabad Telangana Scientific Research Center Al-Ayen University Thi-Qar Iraq

ISBN: (数字)9798350394474

ISBN: (纸本)9798350394481

An ultra-low power DFT architecture suitable for MIMO-OFDM applications & it was introduced in this study. Several radix such as 8/16/32 dependent optimization methods are performed to create variable lengths of 4k/8k points, a necessity in today's 4G and 5G communication technologies, which are plagued by a number of power and performance concerns with DFT processors. these technologies are widely used but have a higher energy footprint than others. Consequently, this work uses a novel approach called "SBOX" and the concept of parallelism to boost performance and reduce power consumption, all of which are essential for an advanced DFT architecture. parallelism and the proposed SBOX model allow for fewer multiplications and faster processing times. Cadence-allegro-17.2 is used for the design and verification of the full implementation; this software is also used for simulation, synthesis, layout, and power analysis. the area required for 8-point s-box DFT is 105.15 um2, it requires 7mW of power, and it can achieve a throughput of 59.33GBPS. In addition, the throughput of 57.33GBPS may be achieved by 16-point s-box DFT with a footprint of 123.35um2, using 9mW of power. Also, the throughput of 32-point s-box DFT is 56.45GBPS on a chip that uses 10.24 mW and occupies 132.35um2. With MIMO in 5G technology, this layout becomes more practical for usage in telecommunications. the performance is enhanced over existing architectures thanks to the optimized radix 8 s-box DFT.

关键词： 5G mobile communication Discrete Fourier transforms Layout Computer architecture parallel processing throughput Software

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Multiple Transform Selection concept modeling and implementation using Interface Based SDF graphs 21

Multiple Transform Selection concept modeling and implementa...

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14th Workshop on Design and architectures for Signal and Image processing, DASIP 2021, held jointly with the 16th HiPEAC conference

作者： Haggui, Naouel Belghith, Fatma Hamidouche, Wassim Masmoudi, Nouri Nezan, Jean-François Ietr Laboratory Insa Rennes France National School of Engineering of Sfax Tunisia

ISBN: (纸本)9781450389013

Recent studies predict that video data accounts for 82% of Internet traffic by 2022. this fact has motivated MPEG to define a new Video Coding Standard called Versatile Video Coding (VVC), which will be released by the end of 2020. VVC will offer the possibility to handle new video formats and to improve significantly video compression over its predecessor HEVC. Indeed, the objective is to reduce the necessary bit rate by half, at equivalent quality. these advances require the use of more complex algorithms, although the increase in complexity has been limited throughout the standardization process. In order to decrease the complexity of VVC and consequently the coding execution time, several methods have been introduced at different stages of the encoder. the aim of this paper is to explore the available parallelism of VVC to accelerate the coding and the decoding processes. this paper focuses on the transformation block and more specifically the new concept of Multiple Transform Selection (MTS) introduced by VVC. Moreover, a study of several granularity levels of Interface-Based Synchronous Dataflow (IBSDF) models and their impact on the performances obtained on x86 architectures is presented. IBSDF dataflow graph has been developed to reveal the available parallelism of MTS. the PREESM fast prototyping tool is then used for the mapping and the scheduling of MTS on virtual and real parallel architectures and for generating efficient parallel implementations on real architectures. PREESM has been used in this work to explore the potential parallelism offered by MTS and to prove the efficiency of MTS on multicore x86 architectures. Experimental results show a speed-up close to the optimum. © 2021 ACM.

关键词： Video signal processing

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PESUnet3+: An Enhanced Unet3+ Network Architecture with parallel Supervised Encoders for Medical Image Segmentation

PESUnet3+: An Enhanced Unet3+ Network Architecture with Para...

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6th international conference on Intelligent Computing and Signal processing (ICSP)

作者： Jiajie Deng Shiyu Hu College of Science Shanghai University Shanghai China

ISBN: (数字)9798350376548

ISBN: (纸本)9798350376555

Recent advancements in medical image segmentation have been significantly propelled by deep learning methodologies, markedly enhancing precision and computational efficacy. this progress is particularly pronounced in the realm of CT scan image processing. Our contribution, PESUnet3+, is an evolved architecture derived from Unet3+, tailored expressly for the segmentation of cancer-related medical imagery. this architecture is distinguished by the integration of sophisticated attention modules and a novel encoder design, which collectively elevate its performance metrics on the Liver Tumor Segmentation (LITS) dataset beyond the conventional Unet3+ framework. A central innovation of PESUnet3+ is its novel hierarchical supervision mechanism within the encoder stage, termed PESM. this mechanism integrates parallel convolutional down-sampling modules with Squeeze-and-Excitation (SE) attention mechanisms to derive supervised attention scores. these scores are subsequently amalgamated with the feature maps from the original down-sampling pathway, thereby augmenting the encoder’ s efficacy. Moreover, the incorporation of an Atrous Spatial Pyramid Pooling (ASPP) module enhances the feature maps at the pinnacle layer, while Selective Kernel (SK) attention modules refine the expressiveness of lower layers. the architecture is further optimized by embedding residual connections within the skip pathways from encoder to decoder, enriching the flow of information. Empirical evaluations conducted on the LITS dataset substantiate PESUnet3+'s superiority, demonstrating a notable increase of 0.0429 in the Dice coefficient compared to its Unet3+ predecessor. Further ablation studies accentuate the pivotal supervisory role of the PESM module, showing substantial improvements in segmentation performance across various networks, with Dice coefficient enhancements ranging from 0.006 to 0.0183.

关键词： Image segmentation Technological innovation Attention mechanisms Computer architecture Signal processing Propulsion Network architecture Distance measurement Biomedical imaging Tumors

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Enhancing Object Detection in Low Light Environments Using Image Enhancement Techniques and YOLO architectures

Enhancing Object Detection in Low Light Environments Using I...

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IEEE international conference on Multi Topic

作者： Syed Muhammad Ammar Ali Jaffri Munim ul Haq Muhammad Farhan Dhanani School of Science and Engineering Habib University Karachi Pakistan

ISBN: (数字)9798331507213

ISBN: (纸本)9798331507220

this study analyzes how YOLO structures and image enhancement techniques can improve object detection in low light conditions. In order to overcome the difficulties caused by glare, noise, and dim lighting, the study makes use of the Exclusively Dark (ExDark) dataset, which covers a wide variety of low light situations. the research showed significant enhancements in object detection precision through the utilization of Convolutional Neural Networks (CNN) and pre-processing techniques. A comparative analysis of YOLO versions v7, v8, and v9 is included in the paper, highlighting the superior performance of YOLO v7 when combined with Enlighten GAN, achieving a mAP 0.5 of 73.7%. the results demonstrate how useful preprocessing methods are when used with YOLO algorithms to provide reliable object detection in difficult low-light situations.

关键词： YOLO Noise Lighting Generative adversarial networks Convolutional neural networks Reliability Image enhancement

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Systolic-Architecture-Based Matrix Multiplications and Its Realization for Multi-Sensor Bias Estimation algorithms

Systolic-Architecture-Based Matrix Multiplications and Its R...

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international conference on Communications, Signal processing and VLSI, IC2SV 2019

作者： Gopala Swamy, B. Sripati Acharya, U. Srihari, P. Pardhasaradhi, B. National Institute of Technology Karnataka Surathkal575025 India

ISBN: (纸本)9789813340572

the accelerators are gaining predominant attention in the HW/SW designs and embedded designs due to the less power consumption and parallel data processing capabilities compared to standard microprocessors and FPGA’s. In this paper, MSSKF (Multi-sensor Schmidt–Kalman filter)-based coupled bias estimation problem is considered for single target multiple sensors case. Here MSSKF augments the state vector and bias vector for bias estimation, results in computationally expensive as the dimensions of the state and sensors increases. Hence to address the computational complexity, digital signal processing (DSP) architectures are proposed and accelerated the algorithm to meet the real-time constraints. In the MSSKF algorithm, the overload of the algorithm is due to state covariance prediction and innovation covariance prediction. To realize the state covariance and innovation covariance, a folded DSP architecture and parallel processing based folded DSP architecture are proposed, respectively. the matrix multiplications are addressed with systolic arrays to gain the advantage of latency and parallel processing. Moreover, MSSKF using systolic array architectures simulated and synthesized in Vivado 2018.1 using Verilog and implemented on FPGA-Zynq-7000 board. the performance of the systolic-based accelerator realization was compared with normal matrix multiplication. © 2021, Springer Nature Singapore Pte Ltd.

关键词： Digital signal processing

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R-GAP: RECURSIVE GRADIENT ATTACK ON PRIVACY 9

R-GAP: RECURSIVE GRADIENT ATTACK ON PRIVACY

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9th international conference on Learning Representations, ICLR 2021

作者： Zhu, Junyi Blaschko, Matthew Dept. ESAT Center for Processing Speech and Images KU Leuven Belgium

Federated learning frameworks have been regarded as a promising approach to break the dilemma between demands on privacy and the promise of learning from large collections of distributed data. Many such frameworks only ask collaborators to share their local update of a common model, i.e. gradients, instead of exposing their raw data to other collaborators. However, recent optimization-based gradient attacks show that raw data can often be accurately recovered from gradients. It has been shown that minimizing the Euclidean distance between true gradients and those calculated from estimated data is often effective in fully recovering private data. However, there is a fundamental lack of theoretical understanding of how and when gradients can lead to unique recovery of original data. Our research fills this gap by providing a closed-form recursive procedure to recover data from gradients in deep neural networks. We name it Recursive Gradient Attack on Privacy (R-GAP). Experimental results demonstrate that R-GAP works as well as or even better than optimization-based approaches at a fraction of the computation under certain conditions. Additionally, we propose a Rank Analysis method, which can be used to estimate the risk of gradient attacks inherent in certain network architectures, regardless of whether an optimization-based or closed-form-recursive attack is used. Experimental results demonstrate the utility of the rank analysis towards improving the network's security. Source code is available for download from https://***/JunyiZhu-AI/R-GAP. © 2021 ICLR 2021 - 9th international conference on Learning Representations. All rights reserved.

关键词： Network architecture

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Multi-Label Text Classification with Transfer Learning

Multi-Label Text Classification with Transfer Learning

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Big Data, Cloud Computing, Data Science & Engineering (BCD)

作者： Likhitha Yelamanchili Ching-Seh Mike Wu Chris Pollett Robert Chun Department of Computer Science San Jose State University San Jose USA

ISBN: (数字)9798350394191

ISBN: (纸本)9798350394207

Multi-label text categorization is a crucial task in Natural Language processing, where each text instance can be simultaneously assigned to numerous labels. In this research, our goal is to assess how well several deep learning models perform on a real-world dataset for multi-label text classification. We employed data augmentation techniques to address the problem of data imbalance and evaluated the effectiveness of several deep learning architectures, as well as fine-tuned pretrained models. We also discovered that models performed better when data augmentation approaches were used. Our study shows that pretrained models are effective for multi-label text classification, with good performance across various metrics. However, the performance may vary on different datasets and require fine-tuning to achieve optimal results. this study also highlights the importance of addressing data imbalance and the potential benefits of using pretrained language models for this task.

关键词： Measurement Deep learning Cloud computing Computational modeling Text categorization Transfer learning Data science Data augmentation Data models Natural language processing

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