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检索条件"任意字段=9th International Conference on Algorithms and Architectures for Parallel Processing"

共 2826 条记录，以下是301-310 订阅

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Temporal Transformation Network Based On Scale Sequences for Cloth-Changing Person Re-Identification in Video Datasets

Temporal Transformation Network Based On Scale Sequences for...

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international conference on Computer and Communications (ICCC)

作者： Xiaoke Zhu Bo Zhao Zhiwei Dong Lingyun Dong Danyang Li School of Computer and Information Engineering Henan University Kaifeng China Henan Engineering Research Center of Intelligent Technology and Application Henan University Henan Key Laboratory of Big Data Analysis and Processing Henan University Kaifeng China

this paper introduces the Temporal Transform Network based on Scale Sequences (TTS) for cloth-changing person re-identification in video datasets. the TTS network is designed to capture multi-scale temporal cues within video sequences. It accomplishes this by initially modeling short-term temporal cues between adjacent frames, followed by capturing long-term relationships between non-consecutive frames. In more detail, short-term temporal cues are modeled through parallel inflated convolutions with different time dilation rates, enabling the representation of pedestrian movement and appearance dynamics. Long-term relationships are effectively captured using a temporal self-attention model, mitigating challenges such as occlusion and noise within the video sequence. the TTS network outperforms existing methods across cloth-changing video ReID datasets such as CCVID. For instance, under general settings, our approach exhibits a 1.1% improvement in top-1 accuracy and a corresponding 1.1% increase in mAP compared to the baseline. In cloth-changing settings, we observe a 0.2% enhancement in top-1 accuracy and a notable 1.3% increase in mAP relative to the baseline.

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Convolutional Neural Network Optimization for Phishing Email Classification

Convolutional Neural Network Optimization for Phishing Email...

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9th IEEE international conference on Big Data (IEEE BigData)

作者： McGinley, Cameron Monroy, Sergio A. Salinas Wichita State Univ Sch Comp Wichita KS 67260 USA

Phishing emails are one of the most common and effective tools that cybercriminals use to gain access to an organization9;s network or personal information. To detect these attacks, email service providers use a va... 详细信息

ISBN: (纸本)9781665439022

Phishing emails are one of the most common and effective tools that cybercriminals use to gain access to an organization's network or personal information. To detect these attacks, email service providers use a variety of tools and indicators, such as the URLs that attackers include in their email messages. However, cybercriminals are able to bypass these detection techniques by omitting URLs in their messages and instead engaging victims in a conversation to advance their attacks. In this paper, we investigate the performance of convolutional neural network (CNN) models that identify phishing attacks by analyzing only the text in the email messages. the models take as input an embedding of the text in the email's body and output a probability indicating the likelihood that the message is malicious. We evaluate several CNN architectures using real-world phishing emails and find that the best performing one can identify phishing attacks with an accuracy of 98.139%, recall of 98.125%, and precision of 98.269%.

关键词： phishing emails deep learning convolutional neural networks word embedding natural language processing

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Accelerating Geo-Distributed Transaction processing with Fast Logging

Accelerating Geo-Distributed Transaction Processing with Fas...

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9th IEEE international conference on Big Data (IEEE BigData)

作者： Ogura, Takuto Akita, Yoshiki Miyazawa, Yuki Kawashima, Hideyuki Mitsubishi UFJ Informat Technol Harumi 2-1-40 Tokyo Japan Keio Univ Fac Environm & Informat Studies Endo 5322 Fujisawa Kanagawa Japan

ISBN: (纸本)9781665439022

We herein propose three novel optimization methods to accelerate distributed transaction processing into a geographically distributed database. the first optimization involves the parallelization of the write-ahead logging protocol. It allows multiple worker threads to synchronize log entries to the storage device simultaneously without any dependencies. the second optimization involves the grouped transfer of log entries from the leader to followers. this reduces the number of transmissions and effectively uses the network bandwidth. the third optimization involves the separation of the worker thread logic. By breaking the logic into the prepare phase and the commit phase, the worker threads at the leader node run asynchronously in parallel without waiting for responses from the follower nodes. the experimental results demonstrated that the proposed method achieved more than 10 million tps and less than 100 ms with client interactions through the network. the CPU utilization was almost 100%, which implied a dramatic reduction in synchronization in worker threads.

关键词： Geo-Distributed Database Distributed Transaction Distributed Consistency Recovery

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A Class of Fast and Accurate Multi-layer Block Summation and Dot Product algorithms 18th

A Class of Fast and Accurate Multi-layer Block Summation a...

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18th IFIP WG 10.3 international conference on Network and parallel Computing, NPC 2021

作者： He, Kang Barrio, Roberto Chen, Lin Jiang, Hao Liu, Jie Gu, Tongxiang Qi, Jin Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha410073 China Department of Applied Mathematics University of Zaragoza ZaragozaE50009 Spain College of Computer National University of Defense Technology Changsha410073 China Institute of Applied Physics and Computational Mathematics Beijing100000 China

ISBN: (纸本)9783030935702

Basic recursive summation and common dot product algorithm have a backward error bound that grows linearly with the vector dimension. Blanchard [1] proposed a class of fast and accurate summation and dot product algorithms respectively called FABsum and FABdot, which trades off the calculation accuracy and speed by the block size. Castaldo [2] proposed a multi-layer block summation and dot product algorithm called SuperBlocksum and SuperBlockdot that can increase the accuracy while adding almost no additional calculations. We combine the idea of [1] with the multi-layer block structure to propose SuperFABsum (for "super fast and accurate block summation") and SuperFABdot (for "super fast and accurate block dot product"). Our algorithms have two variants, one is SuperFAB(within), the other is SuperFAB(outside). Our algorithms further improve accuracy and speed compared with FAB and SuperBlock. We conducted accuracy and speed tests on the high-performance FT2000+ processor. Experimental results show that SuperFABdot(within) algorithm is more accurate than FABdot and SuperBlockdot. Compared with FABdot, SuperFABdot(outside) algorithm can achieve up to 1.2 × performance speedup while ensuring similar accuracy. © 2022, IFIP international Federation for Information processing.

关键词： Artificial intelligence

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Proceedings of the 11th Workshop on parallel Programming and Run-Time Management Techniques for Many-Core architectures / 9th Workshop on Design Tools and architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2020

Proceedings of the 11th Workshop on Parallel Programming and...

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11th Workshop on parallel Programming and Run-Time Management Techniques for Many-Core architectures / 9th Workshop on Design Tools and architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2020

the proceedings contain 5 papers. the topics discussed include: sparse matrix-dense matrix multiplication on heterogeneous CPU+FPGA embedded system;run-time power modelling in embedded GPUs with dynamic voltage and frequency scaling;fault-tolerant online scheduling algorithms for CubeSats;an OpenMP parallel genetic algorithm for design space exploration of heterogeneous multi-processor embedded systems;and automated precision tuning in activity classification systems: a case study.

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A Log-Linear (2+5/6)-Approximation Algorithm for parallel Machine Scheduling with a Single Orthogonal Resource 27th

A Log-Linear (2+5/6)-Approximation Algorithm for Parallel Ma...

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27th international European conference on parallel and Distributed Computing (Euro-Par)

作者： Naruszko, Adrian Przybylski, Bartlomiej Rzadca, Krzysztof Univ Warsaw Inst Informat Warsaw Poland

ISBN: (纸本)9783030856656;9783030856649

As the gap between compute and I/O performance tends to grow, modern High-Performance Computing (HPC) architectures include a new resource type: an intermediate persistent fast memory layer, called burst buffers. this is just one of many kinds of renewable resources which are orthogonal to the processors themselves, such as network bandwidth or software licenses. Ignoring orthogonal resources while making scheduling decisions just for processors may lead to unplanned delays of jobs of which resource requirements cannot be immediately satisfied. We focus on a classic problem of makespan minimization for parallel-machine scheduling of independent sequential jobs with additional requirements on the amount of a single renewable orthogonal resource. We present an easily-implementable log-linear algorithm that we prove is 25/6-approximation. In simulation experiments, we compare our algorithm to standard greedy list-scheduling heuristics and show that, compared to LPT, resource-based algorithms generate significantly shorter schedules.

关键词： parallel machines Orthogonal resource Burst buffers Rigid jobs Approximation algorithm

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Towards Automatic, Predictable and High-Performance parallel Code Generation 30th

Towards Automatic, Predictable and High-Performance Paralle...

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30th international conference on parallel and Distributed processing Techniques, PDPTA 2024, held as part of the World Congress in Computer Science, Computer Engineering and Applied Computing, CSCE 2024

作者： Mullin, Lenore Hains, Gaétan 1400 Washington Ave AlbanyNY12222 United States LACL Université Paris-Est Créteil94000 France

ISBN: (纸本)9783031856372

High-performance architectures have complex features so that reliable production of parallel software is beyond the reach of many Computer Science graduates. Compilers alone cannot guarantee the highest performance and multiple APIs with complex performance features are difficult to master. As a first step towards more comprehensive solutions we are building key elements of a pre-compiler system that will automatically produce predictable, scalable and high-performance code from declarative tensor expressions. In this paper we summarize and analyze a large set of timing experiments of matrix multiplication variants that are mapped to vectorized and multithread code. the analysis covers two high-end target architectures and exhaust a whole space of code, compiler, pragma and parallelism parameters. Our analysis shows how the best choice of parameters is produced from a small set of tests that can converge in a matter of seconds and then predict performance of larger instances to within 25% or much less. Inefficient choices of parameters is also shown to be reliably predicted from small tests, so that our design for a precompiler is guaranteed to be a realistic and portable tool. the generality of our Mathematics of Arrays tensor algebra, and very broad applicability of tensor operations (signal processing, scientific computing, AI, etc.) supports our claim that these experiments and design can be generalized to a general purpose parallel programming tool. © the Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Tensors

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Scalable parallel Static Learning 5

Scalable Parallel Static Learning

引用

5th IEEE international Test conference in Asia (ITC-Asia)

作者： Lin, Xiaoze Lai, Liyang Li, Huawei Shantou Univ Guangdong Prov Key Lab Digital Signal & Image Pro Elect Engn Shantou Guangdong Peoples R China Chinese Acad Sci Inst Comp Technol Beijing Peoples R China

ISBN: (纸本)9781665413343

Static learning is a learning algorithm for finding additional implicit implications between gates in a netlist. In automatic test pattern generation (ATPG) the learned implications help recognize conflicts and redundancies early, and thus greatly improve the performance of ATPG. though ATPG can further benefit from multiple runs of incremental or dynamic learning, it is only feasible when the learning process is fast enough. In the paper, we study speeding up static learning through parallelization on heterogeneous computing platform, which includes multi-core microprocessors (CPUs), and graphics processing units (GPUs). We discuss the advantages and limitations in each of these architectures. With their specific features in mind, we propose two different parallelization strategies that are tailored to multi-core CPUs and GPUs. Speedup and performance scalability of the two proposed parallel algorithms are analyzed. As far as we know, this is the first time that parallel static learning is studied in the literature.

关键词： static learning parallel acceleration GPU multicore CPU

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Desing of image acquisition and processing system based on ZYNQ

Desing of image acquisition and processing system based on Z...

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9th international Symposium on Test Automation & Instrumentation (ISTAI 2022)

作者： Z. Guo J. Zhao S. Yang Tianjin University of Science and Technology Tianjin People's Republic of China

In order to solve the problems of large data image acquisition, stable transmission and real-time processing of moving objects in industrial scenes, a solution of “acquisition + processing + storage + transmission + display” based on FPGA + ARM architecture for Camera Link high-speed camera is proposed. Zynq-7000 series products with abundant logic resources and general CPU are selected. Make full use of the parallel computing capability of the PL side, To solve the problems of high-speed acquisition and image processing, the PS side used to complete the image storage and stable transmission of the system. this paper introduces the key technologies of each part in detail. the experimental results show that the system has the advantages of optimizing image quality, high real-time, no frame loss, small size, low power consumption and low cost. It is also used in high-definition imaging related projects of train body.

关键词： cameras field programmable gate arrays image processing system-on-chip

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PyBONDEM-GPU: A discrete element bonded particle Python research framework – Development and examples 9

PyBONDEM-GPU: A discrete element bonded particle Python rese...

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9th international conference on Micromechanics on Granular Media, Powders and Grains 2021

作者： Dressler, Sven Wilke, Daniel N. Mechanical Engineering Department University of Pretoria Hatfield0083 South Africa

Discrete element modelling (DEM) is widely used to simulate granular systems, nowadays routinely on graphical processing units. Graphics processing units (GPUs) are inherently designed for parallel computation, and recent advances in the architecture, compiler design and language development are allowing general-purpose computation to be computed on multiple GPUs. Application of DEM to bonded particle systems are much less common, with a number of open research questions remaining. this study outlines a Bonded-Particle Research DEM Framework, PyBONDEM-GPU, written in Python. this framework leverages the parallel nature of GPUs for computational speed-up and the rapid prototype flexibility of Python. Python is faster and easier to learn than classical compiled languages, making computational simulation development accessible to undergraduate and graduate engineers. PyBONDEM-GPU leverages the Numba-CUDA module to compile Python syntax for execution on GPUs. the framework enables research of fibre pull-out from fibre-matrix embeddings. Bonds are simulated between all interacting particles. the performance of PyBONDEM-GPU is compared against Python CPU implementations of PyBONDEM using the Numpy and Numba-CPU Python modules. PyBONDEM-GPU was found to be 1000 times faster than the Numpy implementation and 4 times faster than the Numba-CPU implementation to resolve forces and to integrate the equations of motion. © the Authors, published by EDP Sciences.

关键词： Graphics processing unit

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