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检索条件"任意字段=9th International Conference on Algorithms and Architectures for Parallel Processing"

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A precondition generalized minimization residual method based on GPU for static security analysis 9

A precondition generalized minimization residual method base...

引用

9th China international conference on Electricity Distribution, CICED 2021

作者： Qi, Sen Li, Xin Li, Gengfeng Liang, Yi Bie, Zhaohong Tian, Huili Xi'An Jiaotong University China Guangzhou Power Supply Co. Ltd China

ISBN: (纸本)9781728192291

In power system, in order to avoid equipment damage caused by overload and over voltage, fast online real-time static Security analysis (SSA) is very important. With power system expanding constantly, the scale of power grid is getting bigger and bigger, which even reach tens of thousands nodes. therefore, the number of states that need to be calculated is huge, and the traditional serial computing method can't meet the real-time computing requirements of large power grid any more. the expected fault set increases greatly, resulting in a larger computational burden. To solve this problem, A generalized minimization residual method (GMRES) based on GPU for SSA is proposed. First, the SSA is conducted in coarse-grained parallel, and the power flow calculation in each fault case are allocated by thread. then, the solution of the modified equation and the formation of the Jacobian matrix in the process of each power flow are designed in a fine-grained parallel way to improve the computing speed and achieve a better acceleration effect. For the solution of the modified equation, due to its large scale and sparse mode, the iterative method is adopted to solve it. In view of the situation that the Jacobian matrix is asymmetric and positive definite, the internal iteration method adopts the generalized minimization residual (GMRES) method to further accelerate the internal iteration convergence. Incomplete LU precondition method further improves the efficiency of fine grain parallelism. At the same time, the Jacobian matrix with high computing time is parallelized to achieve the best overall acceleration effect. Compared with CPU serial calculation, the acceleration effect of parallel large-scale power system SSA based on GPU can reach a large acceleration ratio, and the acceleration ratio of case2383 power system can reach more than 6.17 times. © 2021 IEEE.

关键词： Graphics processing unit

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High-Performance Simulations on GPUs Using Adaptive Time Steps 20th

High-Performance Simulations on GPUs Using Adaptive Time Ste...

引用

20th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Koester, Marcel Gross, Julian Krueger, Antonio Saarland Informat Campus Campus D3-2 D-66123 Saarbrucken Germany

ISBN: (纸本)9783030602451;9783030602444

Graphics processing Units (GPUs) are widely spread nowadays due to their parallel processing capabilities. Leveraging these hardware features is particularly important for computationally expensive tasks and workloads. Prominent use cases are optimization problems and simulations that can be parallelized and tuned for these architectures. In the general domain of simulations (numerical and discrete), the overall logic is split into several components that are executed one after another. these components need step-size information which determines the number of steps (e.g. the elapsed time) they have to perform. Small step sizes are often required to ensure a valid simulation result with respect to precision and constraint correctness. Unfortunately, they are often the main bottleneck of the simulation. In this paper, we introduce a new and generic way of realizing high-performance simulations with multiple components using adaptive time steps on GPUs. Our method relies on a code-analysis phase that resolves data dependencies between different components. this knowledge is used to generate specially-tuned execution kernels that encapsulate the underlying component logic. An evaluation on our simulation benchmarks shows that we are able to considerably improve runtime performance compared to prior work.

关键词： Simulations parallel computing Adaptive time steps Graphics processing units GPUs

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DETECTION of FERTILE SOILS BASED on SATELLITE IMAGERY processing 9

DETECTION of FERTILE SOILS BASED on SATELLITE IMAGERY PROCES...

引用

9th international conference "Distributed Computing and Grid Technologies in Science and Education", GRID 2021

作者： Grishkin, Valery Zhivulin, Evgeniy Khokhriakova, Anastasiia Karimov, Sardor Saint Petersburg State University 7-9 Universitetskaya nab. Saint Petersburg199034 Russia

the paper proposes a method for detecting fertile soils based on the processing of satellite images. As a result of its application, a map of the location of fertile and infertile soils for a given region of the earth's surface is formed and the corresponding areas are calculated. the method for detecting fertile soils is based on the fact that fertile soil includes areas covered with vegetation in the spring-summer period. therefore, by measuring the spectral characteristics of these areas in the late autumn period, when there is no vegetation on them, it is possible to obtain objective parameters of fertile soils. For detection, a number of classifiers are being built that recognize two classes - fertile soil and sand, which is especially important when monitoring areas prone to desertification. the feature vector used for classification is a set of indices similar to the well-known NDVI index. this set of indices is calculated for each pixel of the image by its values in different spectral channels. Classifiers are implemented using CUDA parallel computing technology on a GPU. Based on the results of the experimental study, a classifier is selected that has shown the best characteristics of the recognition quality. Copyright © 2021 for this paper by its authors. Use permitted under Creative Commons License Attribution 4.0 international (CC BY 4.0).

关键词： Image segmentation

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ParaMoC: A parallel Model Checker for Pushdown Systems 19th

ParaMoC: A Parallel Model Checker for Pushdown Systems

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19th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Wei, Hansheng Ye, Xin Shi, Jianqi Huang, Yanhong East China Normal Univ Natl Trusted Embedded Software Engn Technol Res C Shanghai Peoples R China Res Ctr Hardware Software Codesign Technol & Applicat Eng Shanghai Peoples R China Shanghai Key Lab Trustworthy Comp Shanghai Peoples R China LIPN Paris France Paris Univ 7 Paris France

ISBN: (纸本)9783030389611;9783030389604

Model checking on Pushdown Systems (PDSs) has been extensively used to deal with numerous practical problems. However, the existing model checkers for pushdown systems are executed on the central processing unit (CPU), the performance is hampered by the computing power of the CPU. Compared with the CPU, the graphics processing unit (GPU) has more processing cores, which are suitable and efficient for parallel computing. therefore, it is very attractive to accelerate model checking of PDSs on the GPU. In this paper, we present a new parallel model checker, named ParaMoC, to speed up the performance of model checking problems for pushdown systems (PDSs). Moreover, we focus on how to use Graphics processing Units (GPUs) to accelerate the reachability verification and the LTL model checking of PDSs. the ParaMoC running on a state-of-the-art GPU can be 100 times faster than the traditional PDS model checker.

关键词： Graphics processing unit

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POPULATION ANNEALING MEthOD and HYBRID SUPERCOMPUTER ARCHITECTURE 9

POPULATION ANNEALING METHOD and HYBRID SUPERCOMPUTER ARCHITE...

引用

9th international conference "Distributed Computing and Grid Technologies in Science and Education", GRID 2021

作者： Shchur, Lev Landau Institute for Theoretical Physics Chernogolovka 142432 Russia HSE University Moscow101000 Russia

A population annealing method is a universal algorithm applicable to statistical mechanics systems and optimization problems. It is potentially scalable on any parallel architecture. We review recent developments in the area, emphasizing the implementation of the algorithm on a hybrid parallel program architecture combining CUDA and MPI. the problem is to keep all general-purpose graphics processing unit devices as busy as possible by efficiently redistributing replicas. We provide testing details on hardware-based Intel Skylake/Nvidia V100, running more than two million replicas of the Ising model samples in parallel. As the complexity of the simulated system increases, the acceleration grows toward perfect scalability. this work was done under Grant No. 19-11-00286 from the Russian Science Foundation and was supported in part through computational resources of HPC facilities at HSE University [1]. © 2021 CEUR-WS. All rights reserved.

关键词： Graphics processing unit

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FPGA Based Hardware Accelerator for Sorting Data

FPGA Based Hardware Accelerator for Sorting Data

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Japan-Egypt international conference on Electronics, Communications and Computers (JEC-ECC)

作者： Maher Abdelrasoul Ahmed Sayed Shaban Hala Abdel-Kader Faculty of Engineering Shoubra Benha University Cairo Egypt Institute of Aviation Engineering and Technology Giza Egypt

ISBN: (纸本)9781665482936

Sorting data is one of the most important processes in data processing. Fast processing is urgently needed for real time data access. therefore, hardware accelerator is used to fasten the data processing. In this paper, we present FPGA based hardware accelerators for data sorting using bubble, selection, insertion and merge sorting algorithms. Further, we provide a fair comparison between them in terms of execution time, and area. Our implementations result in that for small data set, merge sort is the best sorting algorithm in terms of execution time. therefore, it can be used as a parallel cooperative system with CPU for high speed data processing.

关键词： Computer architecture Cooperative systems Data processing Real-time systems Hardware acceleration Field programmable gate arrays Sorting

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Tight Bound of parallel Request Latency for Erasure-Coded Distributed Storage System 20th

Tight Bound of Parallel Request Latency for Erasure-Coded Di...

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20th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Zou, Xingshun Li, Wei Shandong Univ Jinan Peoples R China

ISBN: (纸本)9783030602451;9783030602444

With big data analysis and cloud storage improving at an astonishing rate in recent years, more and more parallel computing and data analysis techniques are invented and applied to accessing data from a distributed storage system, which has noticeable differences with accessing data from a separate dedicated storage system. the first and the last processes of a data analysis task in a shared filesystem may have a remarkable gap in latency. the latency of parallel file requests from these processes, however, lacks analytical model especially when erasure code is employed as storage strategy. the main contribution of this work is development of a tight bound of parallel file request latency to give a theoretical upper bound of lantency. Additionally, an exact batch file chunk request analytical model in distributed systems adopting erasure code is studied by the technique of two embedded Markov chains, performance measures such as queue length distribution, waiting time distribution, etc. are derived in closed form. Experimental evaluation verifies accuracy of the theoretical upper bound on latency.

关键词： parallel file requests Distributed storage system Erasure code Queueing theory Latency Embedded Markov chain

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Dielectric Spectroscopy under Extremely High Voltages

Dielectric Spectroscopy under Extremely High Voltages

引用

2022 9th international conference on Condition Monitoring and Diagnosis (CMD)

作者： Keigo Yata Masaki Utagawa Tomohiro Kawashima Yoshinobu Murakami Naohiro Hozumi Toyohashi University of Technology

ISBN: (数字)9784886864314

ISBN: (纸本)9781665470155

the current-integral method (namely, the Q-t method) applies a step-like high voltage to an insulating system and integrates the current response. the response is displayed as a function of time. It has an advantage of reducing noise effects and accurately measuring the conduction current that is normally very weak. the Q-t method proposed at present displays the voltage appearing between two electrodes in the time domain and estimates the displacement current and conduction current from its incline. the transient response of the voltage indicates the process of dielectric polarization, and the frequency response can be obtained by applying appropriate digital signal processing. In this study, to facilitate the Fourier transform, a leakage resistor is connected in parallel with the integrating capacitor, and a finite time constant is given so that the wave tail of the response converges to zero. By normalizing the obtained signal using the transfer function of the system, the results were estimated to be equivalent to the conventional current integration method with an infinite time constant. If the response is recorded over a sufficiently long time, the conduction current can be estimated from this result. At the same time, the frequency dependence of the impedance obtained by signal processing was evaluated. the impedance trajectory and phase spectrum suggest that the boundary between the transient response including the displacement current and the steady-state region of the conduction current can be approximately discriminated. In addition, it was shown that this methodology can estimate the frequency dependence of the complex permittivity under very high voltages.

关键词： Transient response Spectroscopy Frequency dependence Transfer functions High-voltage techniques Digital signal processing Dielectrics

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FPGA Implementation of LDPC Encoder Architecture for Wireless Communication Standards 9

FPGA Implementation of LDPC Encoder Architecture for Wireles...

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9th international conference on Modern Circuits and Systems Technologies (MOCAST)

作者： Goriushkin, Ruslan Nikishkin, Pavel Ovinnikov, Aleksei Likhobabin, Evgeny Vityazev, Vladimir Ryazan State Radio Engn Univ RSREU Dept Telecommun Ryazan Russia Ryazan State Radio Engn Univ RSREU Fdn Radio Engn Ryazan Russia

ISBN: (纸本)9781728166872

In this paper a pipeline architecture is proposed for FPGA implementation of a quasi-cyclic LDPC (QC-LDPC) encoder. the results are provided for implementation on a Xilinx ZYNQ-7 ZC706 Evaluation Board for code with rate 5/6 and block lengths from 576 to 2304. the design is parameterized and can be easily rebuilt to support various code rates and code lengths. the base matrices H and code parameters are taken from the IEEE 802.16e standard. the number of logic elements (LUT), clock speed, and throughput of the encoder are presented for different code lengths. the throughput of up to 16 Gbps for IEEE 802.16e codes has been achieved.

关键词： LDPC QC-LDPC parallel and configurable architectures FPGA implementation encoding

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An open-source, hardware accelerated industry prototype for multidimensional glyphs 14

An open-source, hardware accelerated industry prototype for ...

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14th IADIS international conference Computer Graphics, Visualization, Computer Vision and Image processing 2020, CGVCVIP 2020 and 5th IADIS international conference Big Data Analytics, Data Mining and Computational Intelligence 2020, BigDaCI 2020 and 9th IADIS international conference theory and Practice in Modern Computing 2020, TPMC 2020, Part of the 14th Multi conference on Computer Science and Information Systems, MCCSIS 2020

作者： Rees, Dylan Laramee, Robert S. Swansea University Swansea United Kingdom University of Nottingham Nottingham United Kingdom

ISBN: (纸本)9789898704214

Data-glyphs are a common, useful metaphor for visualizing multidimensional data. However, to represent a larger number of glyphs requires an increasing amount of computational power to derive the data-dependent geometry of each glyph. We present a novel visualization implementation for computing and rendering customized data-glyphs for an industry application. Our software utilizes the parallel processing power of the Graphics processing Unit (GPU) to enable interactive exploration of thousands of multidimensional data-glyphs. this is achieved by passing normalized data values to the OpenGL geometry shader to construct the geometry of each glyph reflecting the data values. the technique is applicable to a variety of glyph designs and supports fast selection between different designs. We demonstrate this technique to render more than 100,000 glyphs at interactive frame rates. To address the challenge of reproducing the technique, we provide a simplified open-source code example implementation that can be used by anyone, including our industry partner. © Proceedings of the 14th IADIS international conference Computer Graphics, Visualization, Computer Vision and Image processing 2020, CGVCVIP 2020 and Proceedings of the 5th IADIS international conference Big Data Analytics, Data Mining and Computational Intelligence 2020, BigDaCI 2020 and Proceedings of the 9th IADIS international conference theory and Practice in Modern Computing 2020, TPMC 2020 - Part of the 14th Multi conference on Computer Science and Information Systems, MCCSIS 2020. All rights reserved.

关键词： Graphics processing unit

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