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Multi-Stream LDPC Decoder on GPU of Mobile Devices 9

Multi-Stream LDPC Decoder on GPU of Mobile Devices

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9th IEEE Annual Computing and Communication Workshop and conference (CCWC)

作者： Amiri, Roohollah Mehrpouyan, Hani Boise State Univ Elect & Comp Engn Boise ID 83725 USA

ISBN: (纸本)9781728105543

Low-density parity check (LDPC) codes have been extensively applied in mobile communication systems due to their excellent error correcting capabilities. However, their broad adoption has been hindered by the high complexity of the LDPC decoder. Although to date, dedicated hardware has been used to implement low latency LDPC decoders, recent advancements in the architecture of mobile processors have made it possible to develop software solutions. In this paper, we propose a multi-stream LDPC decoder designed for a mobile device. the proposed decoder uses graphics processing unit (GPU) of a mobile device to achieve efficient real-time decoding. the proposed solution is implemented on an NVIDIA Tegra board as a system on a chip (SoC), where our results indicate that we can control the load on the central processing units through the multi-stream structure.

关键词： parallel and Distributed algorithms Multiprocessor architectures LDPC Decoder GPU processing

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Vectorized parallel solver for tridiagonal toeplitz systems of linear equations 1

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13th international conference on parallel processing and Applied Mathematics, PPAM 2019

作者： Dmitruk, Beata Stpiczyński, Przemyslaw Institute of Computer Science Maria Curie–Sklodowska University ul. Akademicka 9 Lublin20-033 Poland

ISBN: (数字)9783030432294

ISBN: (纸本)9783030432287

the aim of this paper is to present two versions of a new divide and conquer parallel algorithm for solving tridiagonal Toeplitz systems of linear equations. Our new approach is based on a recently developed algorithm for solving linear recurrence systems. We discuss how to reduce the number of necessary synchronizations and show proper data layout that allows to use cache memory and SIMD extensions of modern processors. Numerical experiments show that our new implementations achieve very good seedup on multicore and manycore architectures. Moreover, they are more energy efficient than a simple sequential algorithm. © Springer Nature Switzerland AG 2020.

关键词： Energy efficiency

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ASIC Implementation of Fixed-Point Iterative, parallel, and Pipeline CORDIC Algorithm 8th

ASIC Implementation of Fixed-Point Iterative, Parallel, and ...

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8th international conference on Soft Computing for Problem Solving (SocProS)

作者： Jyothi, Grande Naga Debanjan, Kundu Anusha, Gorantla VIT Univ Vellore Tamil Nadu India GCT Coimbatore Coimbatore Tamil Nadu India

ISBN: (纸本)9789811500350;9789811500343

In this paper, we proposed a Coordinate Rotation Digital Computer (CORDIC) algorithm for efficient hardware implementation of mathematical functions which can be carried out in a wide variety of ways for many digital signal processing applications. the CORDIC is a single unified algorithm for calculating many elementary functions such as trigonometric, hyperbolic, logarithmic function, exponential functions, multiplication, division, and so on. In this paper, a novel low power, low area, and high throughput fixed-point CORDIC algorithms are proposed. the standard CORDIC is also implemented for comparing the synthesis results. the proposed architecture scaling has been done using low area and low-power Scale Factor Correction Unit (SFCU). A low ADP SQRT-CSLA based ADD/SUB unit is proposed to overcomed the disadvantages of the basic ADD/SUB unit used in the standard CORDIC. the ROM lookup table size is also reduced to half. Extensive simulations are performed to verify the functionality. the standard and proposed CORDIC architectures are simulated in cadence NC launch and synthesized in cadence RC tool using TSMC GPDK 45 nm technology and area, power, and delay are calculated. the area and power consumption of the proposed CORDIC architecture are less when compared with standard CORDIC design.

关键词： CORDIC algorithm Pipeline parallel Digital signal processing

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Performance Analysis of parallel FIR Digital Filter Based on Even Symmetric Fast FIR Algorithm using Different Adders

Performance Analysis of Parallel FIR Digital Filter Based on...

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international conference of Electronics, Communication and Aerospace Technology (ICECA)

作者： S Narendran B T Geetha Institute of Electronics and Communication Engineering Saveetha School of Engineering SIMATS Chennai India

ISBN: (纸本)9781665435253

the ultimate goal of the research work is to analyze the performance of FIR filter designed based on FFA algorithm. the proposed structure aims at area-optimized adders which are designed for symmetric coefficient that reduces hardware cost in the design with a constrain that the filter tap is of even order. Area analysis of silicon chip is performed using different adders like Ripple Carry Adder (RCA), Carry Look-Ahead Adder (CLA) and Conditional Sum Adder (COS). Performance analysis report for a 3 parallel 96-tap filter is considered based on the above adder, where the RCA requires less area utilization compared to other three adders. the symmetric convolution-based RCA Fast FIR Algorithm (FFA) structure requires only 896 slices whereas COS requires 1024 slices and CLA requires 960 slices. For higher-order, FIR filter structure of 1024 or higher taps, the savings in the area utilization for RCA based FFA is approximately 10% and 15% compared to CLA and COS basedFFA respectively because COS requires more hardware building blocks. the RCA based FFA increases the latency by approximately 9% and 7% compared to CLA and COS based FFA respectively, and there will be a trade-off.

关键词： Costs Finite impulse response filters Signal processing algorithms Digital signal processing Filtering algorithms Approximation algorithms Hardware

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9th CCF international conference on Natural Language processing and Chinese Computing, NLPCC 2020

9th CCF International Conference on Natural Language Process...

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9th CCF international conference on Natural Language processing and Chinese Computing, NLPCC 2020

ISBN: (纸本)9783030604561

the proceedings contain 114 papers. the special focus in this conference is on Natural Language processing and Chinese Computing. the topics include: Joint Bilinear End-to-End Dependency Parsing with Prior Knowledge;multi-layer Joint Learning of Chinese Nested Named Entity Recognition Based on Self-attention Mechanism;Adversarial BiLSTM-CRF architectures for Extra-Propositional Scope Resolution;analyzing Relational Semantics of Clauses in Chinese Discourse Based on Feature Structure;efficient Lifelong Relation Extraction with Dynamic Regularization;collective Entity Disambiguation Based on Deep Semantic Neighbors andHeterogeneous Entity Correlation;boosting Cross-lingual Entity Alignment with Textual Embedding;label Embedding Enhanced Multi-label Sequence Generation Model;ensemble Distilling Pretrained Language Models for Machine Translation Quality Estimation;the Sentencing-Element-Aware Model for Explainable Term-of-Penalty Prediction;weaken Grammatical Error Influence in Chinese Grammatical Error Correction;encoding Sentences with a Syntax-Aware Self-attention Neural Network forEmotion Distribution Prediction;hierarchical Multi-view Attention for Neural Review-Based Recommendation;negative Feedback Aware Hybrid Sequential Neural Recommendation Model;MSReNet: Multi-step Reformulation for Open-Domain Question Answering;prophetNet-Ads: A Looking Ahead Strategy for Generative Retrieval Models in Sponsored Search Engine;LARQ: Learning to Ask and Rewrite Questions for Community Question Answering;abstractive Summarization via Discourse Relation and Graph Convolutional Networks;Chinese Question Classification Based on ERNIE and Feature Fusion;an Abstractive Summarization Method Based on Global Gated Dual Encoder;referring Expression Generation viaVisual Dialogue;rumor Detection on Hierarchical Attention Network with User and Sentiment Information;measuring the Semantic Stability of Word Embedding;task-to-Task Transfer Learning with Parameter-Efficient Adapter;key-Elemen

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9th CCF international conference on Natural Language processing and Chinese Computing, NLPCC 2020

9th CCF International Conference on Natural Language Process...

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9th CCF international conference on Natural Language processing and Chinese Computing, NLPCC 2020

ISBN: (纸本)9783030604493

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A New Partially-parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio 33

A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic L...

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33rd IEEE international conference on VLSI Design / 19th international conference on Embedded Systems

作者： Verma, Anuj Shrestha, Rahul Indian Inst Technol Mandi Sch Comp & Elect Engn Suran Himachal Prades India

ISBN: (数字)9781728157016

ISBN: (纸本)9781728157016

this paper presents partially-parallel low-density parity-check (LDPC) decoder architecture for binary-input additive-white Gaussian-noise (BIAWGN) channel in 5G new-radio cellular-communication technology based on layered min-sum decoding algorithm. this architecture exploits the iterative decomposition of check node and variable-node combined-processing unit which leads to area optimization and lower hardware complexity. the proposed VLSI architecture of LDPC decoder processes quasi-cyclic LDPC encoded information which is received as log-likelihood ratios (LLRs) from soft demodulator at the receiver side. It achieves the adequate bit-error-rate (BER) of 10(-6) between 2 to 4 dB of bit-energy to noise-power-spectral density (E-b/N-o) with 10 decoding iterations for various code rates like 1/3, 2/5, 1/2, 2/3, 3/4, 5/6, and 8/9. the VLSI architecture of 5G new-radio LDPC decoder has been field-programmable logic-array (FPGA) prototyped and its implementation results are compared with state-of-the-art designs where the proposed LDPC decoder shows lower hardware utilization up to 87%. To the best of our knowledge, this is the first VLSI-architecture of LDPC decoder reported for 5G new-radio compliant to the specifications of enhanced mobile broadband (eMBB).

关键词： Wireless communication LDPC code channel decoder layered min-sum decoding 5G new radio digital very-large-scale-integration (VLSI) architectures and field-programmable gate-array (FPGA)

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Pipeline Architecture for N==K*2L Bit Modular ALU: Case Study between Current Generation Computing and Vedic Computing

Pipeline Architecture for N==K*2L Bit Modular ALU: Case Stud...

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international conference for Convergence of Technology (I2CT)

作者： G.N. Chiranjeevi Subhash Kulkarni Department of Electronics and Communication Engineering PESIT-Bangalore South Campus Bangalore Affiliated to Visvesvaraya Technological University Belagavi Karnataka India

ISBN: (纸本)9781728188768;9781728188775

this paper describes a design architecture that performs mathematical operations using Vedic sutra for upward compatibility in pipeline manner. In spite of increasing the area, performance and reducing power, Vedic architecture have observed to be inherently compatible with higher efficiency for pipeline architecture. However Vedic architecture leads to additional flexibility starting from 2-bit base modules to 8-bit modules (L=1,2,3) and pipeline can be compactable to any base modules for any given length. Many researchers proposed arithmetic algorithms at simulation level using vedic sutra. these algorithm have been evaluated with better performance, area and speed. the literature has been widely found to be towards individual arithmetical operators like multiplier, square and cube and so on. A consolidated computing architecture, especially N-bit ALU is yet be realized Generalized N-bit ALU, can always be realized using pipeline modular architecture. the proposition is on realizing N-bit using `2^L, as base modules using `K' modules in pipelining. the authors have extensively verified modular architecture for 4-Bit modules for 16 bit and 32 bit pipelined operations. Individually multiplication using Urdhva Tiryakbhyam, division using Dhwajanka sutra, square using Dwandwayoga sutra. MAC unit which involves multiplication algorithms used in FFT and IFFT using sutras of Vedic mathematics and it is possible to achieve reduce version interms of speed and delay, compared to different generations of ALU the authors are now exploring N-bit ALU architecture FPGA implementation using Vedic sutras with flexible modular pipeline architecture and mainly targeted for Digital Signal processing applications.

关键词： Computational modeling Signal processing algorithms Process control Computer architecture Digital signal processing parallel architectures Delays

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Generic methodology for the design of parallel algorithms based on pattern languages 9th

Generic methodology for the design of parallel algorithms ba...

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9th international conference on Supercomputing, ISUM 2018

作者： Serrano-Rubio, A. Alejandra Meneses-Viveros, Amilcar Morales-Luna, Guillermo B. Paredes-López, Mireya Computer Science Department Cinvestav-IPN Mexico City Mexico Mathematics Department Cinvestav-IPN Mexico City Mexico

ISBN: (纸本)9783030104474

A parallel system to solve complex computational problems involve multiple instruction, simultaneous flows, communication structures, synchronisation and competition conditions between processes, as well as mapping and balance of workload in each processing unit. the algorithm design and the facilities of processing units will affect the cost-performance ratio of any algorithm. We propose a generic methodology to capture the main characteristics of parallel algorithm design methodologies, and to add the experience of expert programmers through pattern languages. Robust design considering the relations between architectures and programs is a crucial item to implement high-quality parallel algorithms. We aim for a methodology to exploit algorithmic concurrencies and to establish optimal process allocation into processing units, exploring the lowest implementation details. Some basic examples are described, such as the k-means algorithm, to illustrate and to show the effectiveness of our methodology. Our proposal identifies essential design patterns to find models of Data Mining algorithms with string self-adaptive mechanisms for homogeneous and heterogeneous parallel architectures. © Springer Nature Switzerland AG 2019.

关键词： parallel algorithms

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Hardware Accelerated ATLAS Workloads on the WLCG Grid 19

Hardware Accelerated ATLAS Workloads on the WLCG Grid

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19th international Workshop on Advanced Computing and Analysis Techniques in Physics Research (ACAT)

作者： Forti, A. C. Heinrich, L. Guth, M. Univ Manchester Sch Phys & Astron Oxford Rd Manchester M13 9PL Lancs England CERN European Lab Particle Phys Rue Geneve 23 CH-1211 Geneva Switzerland Albert Ludwigs Univ Freiburg Friedrichstr 39 D-79085 Freiburg Germany

In recent years the usage of machine learning techniques within data-intensive sciences in general and high-energy physics in particular has rapidly increased, in part due to the availability of large datasets on which such algorithms can be trained, as well as suitable hardware, such as graphic or tensor processing units, which greatly accelerate the training and execution of such algorithms. Within the HEP domain, the development of these techniques has so far relied on resources external to the primary computing infrastructure of the WLCG (Worldwide LHC Computing Grid). In this paper we present an integration of hardware-accelerated workloads into the Grid through the declaration of dedicated queues with access to hardware accelerators and the use of Linux container images holding a modern data science software stack. A frequent use-case in the development of machine learning algorithms is the optimization of neural networks through the tuning of their Hyper Parameters (HP). For this often a large range of network variations must be trained and compared, which for some optimization schemes can be performed in parallel - a workload well suited for Grid computing. An example of such a hyper-parameter scan on Grid resources for the case of flavor tagging within ATLAS is presented.

关键词： High energy physics

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